1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef VIRTIO_GPU_HW_H 20 #define VIRTIO_GPU_HW_H 21 #include <linux/types.h> 22 #define VIRTIO_GPU_F_VIRGL 0 23 #define VIRTIO_GPU_F_EDID 1 24 enum virtio_gpu_ctrl_type { 25 VIRTIO_GPU_UNDEFINED = 0, 26 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 27 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 28 VIRTIO_GPU_CMD_RESOURCE_UNREF, 29 VIRTIO_GPU_CMD_SET_SCANOUT, 30 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 31 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 32 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 33 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 34 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 35 VIRTIO_GPU_CMD_GET_CAPSET, 36 VIRTIO_GPU_CMD_GET_EDID, 37 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 38 VIRTIO_GPU_CMD_CTX_DESTROY, 39 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 40 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 41 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 42 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 43 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 44 VIRTIO_GPU_CMD_SUBMIT_3D, 45 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 46 VIRTIO_GPU_CMD_MOVE_CURSOR, 47 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 48 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 49 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 50 VIRTIO_GPU_RESP_OK_CAPSET, 51 VIRTIO_GPU_RESP_OK_EDID, 52 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 53 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 54 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 55 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 56 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 57 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 58 }; 59 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 60 struct virtio_gpu_ctrl_hdr { 61 __le32 type; 62 __le32 flags; 63 __le64 fence_id; 64 __le32 ctx_id; 65 __le32 padding; 66 }; 67 struct virtio_gpu_cursor_pos { 68 __le32 scanout_id; 69 __le32 x; 70 __le32 y; 71 __le32 padding; 72 }; 73 struct virtio_gpu_update_cursor { 74 struct virtio_gpu_ctrl_hdr hdr; 75 struct virtio_gpu_cursor_pos pos; 76 __le32 resource_id; 77 __le32 hot_x; 78 __le32 hot_y; 79 __le32 padding; 80 }; 81 struct virtio_gpu_rect { 82 __le32 x; 83 __le32 y; 84 __le32 width; 85 __le32 height; 86 }; 87 struct virtio_gpu_resource_unref { 88 struct virtio_gpu_ctrl_hdr hdr; 89 __le32 resource_id; 90 __le32 padding; 91 }; 92 struct virtio_gpu_resource_create_2d { 93 struct virtio_gpu_ctrl_hdr hdr; 94 __le32 resource_id; 95 __le32 format; 96 __le32 width; 97 __le32 height; 98 }; 99 struct virtio_gpu_set_scanout { 100 struct virtio_gpu_ctrl_hdr hdr; 101 struct virtio_gpu_rect r; 102 __le32 scanout_id; 103 __le32 resource_id; 104 }; 105 struct virtio_gpu_resource_flush { 106 struct virtio_gpu_ctrl_hdr hdr; 107 struct virtio_gpu_rect r; 108 __le32 resource_id; 109 __le32 padding; 110 }; 111 struct virtio_gpu_transfer_to_host_2d { 112 struct virtio_gpu_ctrl_hdr hdr; 113 struct virtio_gpu_rect r; 114 __le64 offset; 115 __le32 resource_id; 116 __le32 padding; 117 }; 118 struct virtio_gpu_mem_entry { 119 __le64 addr; 120 __le32 length; 121 __le32 padding; 122 }; 123 struct virtio_gpu_resource_attach_backing { 124 struct virtio_gpu_ctrl_hdr hdr; 125 __le32 resource_id; 126 __le32 nr_entries; 127 }; 128 struct virtio_gpu_resource_detach_backing { 129 struct virtio_gpu_ctrl_hdr hdr; 130 __le32 resource_id; 131 __le32 padding; 132 }; 133 #define VIRTIO_GPU_MAX_SCANOUTS 16 134 struct virtio_gpu_resp_display_info { 135 struct virtio_gpu_ctrl_hdr hdr; 136 struct virtio_gpu_display_one { 137 struct virtio_gpu_rect r; 138 __le32 enabled; 139 __le32 flags; 140 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 141 }; 142 struct virtio_gpu_box { 143 __le32 x, y, z; 144 __le32 w, h, d; 145 }; 146 struct virtio_gpu_transfer_host_3d { 147 struct virtio_gpu_ctrl_hdr hdr; 148 struct virtio_gpu_box box; 149 __le64 offset; 150 __le32 resource_id; 151 __le32 level; 152 __le32 stride; 153 __le32 layer_stride; 154 }; 155 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 156 struct virtio_gpu_resource_create_3d { 157 struct virtio_gpu_ctrl_hdr hdr; 158 __le32 resource_id; 159 __le32 target; 160 __le32 format; 161 __le32 bind; 162 __le32 width; 163 __le32 height; 164 __le32 depth; 165 __le32 array_size; 166 __le32 last_level; 167 __le32 nr_samples; 168 __le32 flags; 169 __le32 padding; 170 }; 171 struct virtio_gpu_ctx_create { 172 struct virtio_gpu_ctrl_hdr hdr; 173 __le32 nlen; 174 __le32 padding; 175 char debug_name[64]; 176 }; 177 struct virtio_gpu_ctx_destroy { 178 struct virtio_gpu_ctrl_hdr hdr; 179 }; 180 struct virtio_gpu_ctx_resource { 181 struct virtio_gpu_ctrl_hdr hdr; 182 __le32 resource_id; 183 __le32 padding; 184 }; 185 struct virtio_gpu_cmd_submit { 186 struct virtio_gpu_ctrl_hdr hdr; 187 __le32 size; 188 __le32 padding; 189 }; 190 #define VIRTIO_GPU_CAPSET_VIRGL 1 191 #define VIRTIO_GPU_CAPSET_VIRGL2 2 192 struct virtio_gpu_get_capset_info { 193 struct virtio_gpu_ctrl_hdr hdr; 194 __le32 capset_index; 195 __le32 padding; 196 }; 197 struct virtio_gpu_resp_capset_info { 198 struct virtio_gpu_ctrl_hdr hdr; 199 __le32 capset_id; 200 __le32 capset_max_version; 201 __le32 capset_max_size; 202 __le32 padding; 203 }; 204 struct virtio_gpu_get_capset { 205 struct virtio_gpu_ctrl_hdr hdr; 206 __le32 capset_id; 207 __le32 capset_version; 208 }; 209 struct virtio_gpu_resp_capset { 210 struct virtio_gpu_ctrl_hdr hdr; 211 __u8 capset_data[]; 212 }; 213 struct virtio_gpu_cmd_get_edid { 214 struct virtio_gpu_ctrl_hdr hdr; 215 __le32 scanout; 216 __le32 padding; 217 }; 218 struct virtio_gpu_resp_edid { 219 struct virtio_gpu_ctrl_hdr hdr; 220 __le32 size; 221 __le32 padding; 222 __u8 edid[1024]; 223 }; 224 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 225 struct virtio_gpu_config { 226 __u32 events_read; 227 __u32 events_clear; 228 __u32 num_scanouts; 229 __u32 num_capsets; 230 }; 231 enum virtio_gpu_formats { 232 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 233 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 234 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 235 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 236 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 237 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 238 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 239 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 240 }; 241 #endif 242