1 /* 2 * Copyright (C) 2019 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __LOCAL_POC_H__ 18 #define __LOCAL_POC_H__ 19 20 #define DRM_IOCTL_BASE 'd' 21 #define DRM_IOW(nr, type) _IOW(DRM_IOCTL_BASE, nr, type) 22 #define DRM_IOWR(nr, type) _IOWR(DRM_IOCTL_BASE, nr, type) 23 24 #define DRM_COMMAND_BASE 0x40 25 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000 26 27 /* reserved object handles when using deprecated object APIs - these 28 * are here so that libdrm can allow interoperability with the new 29 * object APIs 30 */ 31 #define NOUVEAU_ABI16_CLIENT 0xffffffff 32 #define NOUVEAU_ABI16_DEVICE 0xdddddddd 33 #define NOUVEAU_ABI16_CHAN(n) (0xcccc0000 | (n)) 34 35 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 36 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 37 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 38 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 39 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) 40 41 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ 42 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 43 #define NOUVEAU_GEM_TILE_16BPP 0x00000001 44 #define NOUVEAU_GEM_TILE_32BPP 0x00000002 45 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 46 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 47 48 struct drm_nouveau_gem_info { 49 uint32_t handle; 50 uint32_t domain; 51 uint64_t size; 52 uint64_t offset; 53 uint64_t map_handle; 54 uint32_t tile_mode; 55 uint32_t tile_flags; 56 }; 57 58 struct drm_nouveau_gem_new { 59 struct drm_nouveau_gem_info info; 60 uint32_t channel_hint; 61 uint32_t align; 62 }; 63 64 struct drm_nouveau_gem_set_tiling { 65 uint32_t handle; 66 uint32_t tile_mode; 67 uint32_t tile_flags; 68 }; 69 70 #define NOUVEAU_GEM_MAX_BUFFERS 1024 71 struct drm_nouveau_gem_pushbuf_bo_presumed { 72 uint32_t valid; 73 uint32_t domain; 74 uint64_t offset; 75 }; 76 77 struct drm_nouveau_gem_pushbuf_bo { 78 uint64_t user_priv; 79 uint32_t handle; 80 uint32_t read_domains; 81 uint32_t write_domains; 82 uint32_t valid_domains; 83 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 84 }; 85 86 #define NOUVEAU_GEM_RELOC_LOW (1 << 0) 87 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 88 #define NOUVEAU_GEM_RELOC_OR (1 << 2) 89 #define NOUVEAU_GEM_MAX_RELOCS 1024 90 struct drm_nouveau_gem_pushbuf_reloc { 91 uint32_t reloc_bo_index; 92 uint32_t reloc_bo_offset; 93 uint32_t bo_index; 94 uint32_t flags; 95 uint32_t data; 96 uint32_t vor; 97 uint32_t tor; 98 }; 99 100 #define NOUVEAU_GEM_MAX_PUSH 512 101 struct drm_nouveau_gem_pushbuf_push { 102 uint32_t bo_index; 103 uint32_t pad; 104 uint64_t offset; 105 uint64_t length; 106 }; 107 108 struct drm_nouveau_gem_pushbuf { 109 uint32_t channel; 110 uint32_t nr_buffers; 111 uint64_t buffers; 112 uint32_t nr_relocs; 113 uint32_t nr_push; 114 uint64_t relocs; 115 uint64_t push; 116 uint32_t suffix0; 117 uint32_t suffix1; 118 uint64_t vram_available; 119 uint64_t gart_available; 120 }; 121 122 #define NOUVEAU_GEM_PUSHBUF_2_FENCE_WAIT 0x00000001 123 #define NOUVEAU_GEM_PUSHBUF_2_FENCE_EMIT 0x00000002 124 struct drm_nouveau_gem_pushbuf_2 { 125 uint32_t channel; 126 uint32_t flags; 127 uint32_t nr_push; 128 uint32_t nr_buffers; 129 int32_t fence; /* in/out, depends on flags */ 130 uint32_t pad; 131 uint64_t push; /* in raw hw format */ 132 uint64_t buffers; /* ptr to drm_nouveau_gem_pushbuf_bo */ 133 uint64_t vram_available; 134 uint64_t gart_available; 135 }; 136 137 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 138 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 139 struct drm_nouveau_gem_cpu_prep { 140 uint32_t handle; 141 uint32_t flags; 142 }; 143 144 struct drm_nouveau_gem_cpu_fini { 145 uint32_t handle; 146 }; 147 148 struct drm_nouveau_gem_as_alloc { 149 uint64_t pages; /* in, page length */ 150 uint32_t page_size; /* in, byte page size */ 151 #define NOUVEAU_GEM_AS_SPARSE 0x1 152 uint32_t flags; 153 uint64_t align; /* in, requested alignment in bytes */ 154 uint64_t address; /* in/out, non-zero for fixed address allocation */ 155 }; 156 157 struct drm_nouveau_gem_as_free { 158 uint64_t address; /* in, byte address */ 159 }; 160 161 #define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT 8 162 #define NOUVEAU_GEM_CHANNEL_GR_ERROR_SW_NOTIFY 13 163 #define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31 164 #define NOUVEAU_GEM_CHANNEL_PBDMA_ERROR 32 165 struct drm_nouveau_gem_set_error_notifier { 166 uint32_t channel; 167 uint32_t buffer; 168 uint32_t offset; /* bytes, u32-aligned */ 169 }; 170 171 struct drm_nouveau_gem_map { 172 uint32_t handle; 173 uint32_t domain; 174 uint64_t offset; 175 uint64_t delta; 176 uint64_t length; 177 uint32_t tile_mode; 178 uint32_t tile_flags; 179 }; 180 181 struct drm_nouveau_gem_unmap { 182 uint32_t handle; 183 uint32_t pad; 184 uint64_t offset; 185 uint64_t delta; 186 uint64_t length; 187 }; 188 189 struct nvif_ioctl_v0 { 190 __u8 version; 191 #define NVIF_IOCTL_V0_OWNER_NVIF 0x00 192 #define NVIF_IOCTL_V0_OWNER_ANY 0xff 193 __u8 owner; 194 #define NVIF_IOCTL_V0_NOP 0x00 195 #define NVIF_IOCTL_V0_SCLASS 0x01 196 #define NVIF_IOCTL_V0_NEW 0x02 197 #define NVIF_IOCTL_V0_DEL 0x03 198 #define NVIF_IOCTL_V0_MTHD 0x04 199 #define NVIF_IOCTL_V0_RD 0x05 200 #define NVIF_IOCTL_V0_WR 0x06 201 #define NVIF_IOCTL_V0_MAP 0x07 202 #define NVIF_IOCTL_V0_UNMAP 0x08 203 #define NVIF_IOCTL_V0_NTFY_NEW 0x09 204 #define NVIF_IOCTL_V0_NTFY_DEL 0x0a 205 #define NVIF_IOCTL_V0_NTFY_GET 0x0b 206 #define NVIF_IOCTL_V0_NTFY_PUT 0x0c 207 __u8 type; 208 __u8 path_nr; 209 #define NVIF_IOCTL_V0_ROUTE_NVIF 0x00 210 #define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff 211 __u8 pad04[3]; 212 __u8 route; 213 __u64 token; 214 __u32 path[8]; /* in reverse */ 215 __u8 data[]; /* ioctl data (below) */ 216 }; 217 218 #define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */ 219 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */ 220 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */ 221 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */ 222 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */ 223 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */ 224 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */ 225 #define DRM_NOUVEAU_NVIF 0x07 226 #define DRM_NOUVEAU_GEM_NEW 0x40 227 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 228 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 229 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 230 #define DRM_NOUVEAU_GEM_INFO 0x44 231 /* 232 * range (0x50+DRM_COMMAND_BASE)..DRM_COMMAND_END is reserved for staging, 233 * unstable ioctls 234 */ 235 #define DRM_NOUVEAU_STAGING_IOCTL 0x50 236 #define DRM_NOUVEAU_GEM_SET_TILING (DRM_NOUVEAU_STAGING_IOCTL + 0x0) 237 #define DRM_NOUVEAU_GEM_PUSHBUF_2 (DRM_NOUVEAU_STAGING_IOCTL + 0x1) 238 #define DRM_NOUVEAU_GEM_SET_INFO (DRM_NOUVEAU_STAGING_IOCTL + 0x2) 239 #define DRM_NOUVEAU_GEM_AS_ALLOC (DRM_NOUVEAU_STAGING_IOCTL + 0x3) 240 #define DRM_NOUVEAU_GEM_AS_FREE (DRM_NOUVEAU_STAGING_IOCTL + 0x4) 241 #define DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER (DRM_NOUVEAU_STAGING_IOCTL + 0x5) 242 #define DRM_NOUVEAU_GEM_MAP (DRM_NOUVEAU_STAGING_IOCTL + 0x6) 243 #define DRM_NOUVEAU_GEM_UNMAP (DRM_NOUVEAU_STAGING_IOCTL + 0x7) 244 245 #define DRM_IOCTL_NOUVEAU_GEM_NEW \ 246 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 247 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF \ 248 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, \ 249 struct drm_nouveau_gem_pushbuf) 250 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP \ 251 DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, \ 252 struct drm_nouveau_gem_cpu_prep) 253 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI \ 254 DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, \ 255 struct drm_nouveau_gem_cpu_fini) 256 #define DRM_IOCTL_NOUVEAU_GEM_INFO \ 257 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) 258 #define DRM_IOCTL_NOUVEAU_GEM_SET_TILING \ 259 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_TILING, \ 260 struct drm_nouveau_gem_set_tiling) 261 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF_2 \ 262 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF_2, \ 263 struct drm_nouveau_gem_pushbuf_2) 264 #define DRM_IOCTL_NOUVEAU_GEM_SET_INFO \ 265 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_INFO, \ 266 struct drm_nouveau_gem_info) 267 #define DRM_IOCTL_NOUVEAU_GEM_AS_ALLOC \ 268 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_AS_ALLOC, \ 269 struct drm_nouveau_gem_as_alloc) 270 #define DRM_IOCTL_NOUVEAU_GEM_AS_FREE \ 271 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_AS_FREE, \ 272 struct drm_nouveau_gem_as_free) 273 #define DRM_IOCTL_NOUVEAU_GEM_SET_ERROR_NOTIFIER \ 274 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER, \ 275 struct drm_nouveau_gem_set_error_notifier) 276 #define DRM_IOCTL_NOUVEAU_GEM_MAP \ 277 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_MAP, struct drm_nouveau_gem_map) 278 #define DRM_IOCTL_NOUVEAU_GEM_UNMAP \ 279 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_UNMAP, \ 280 struct drm_nouveau_gem_unmap) 281 282 #define DRM_IOCTL_NOUVEAU_NVIF \ 283 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NVIF, struct nvif_ioctl_v0) 284 285 #endif 286