1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _MSM_MDP_H_ 20 #define _MSM_MDP_H_ 21 #include <stdint.h> 22 #include <linux/fb.h> 23 #define MSMFB_IOCTL_MAGIC 'm' 24 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 25 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 26 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 27 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 28 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 29 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 30 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 31 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 32 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 33 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) 34 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 35 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) 36 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 37 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) 38 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) 39 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) 40 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 41 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) 42 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 43 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) 44 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 45 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 46 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) 47 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) 48 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) 49 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 50 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 51 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 52 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) 53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) 54 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 55 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 56 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 57 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 58 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 59 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 60 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) 61 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 62 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 63 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) 64 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 65 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) 66 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 67 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, struct mdp_pp_feature_version) 68 #define FB_TYPE_3D_PANEL 0x10101010 69 #define MDP_IMGTYPE2_START 0x10000 70 #define MSMFB_DRIVER_VERSION 0xF9E8D701 71 #define MDP_IMGTYPE_END 0x100 72 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 73 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 74 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 75 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 76 #define IS_MDSS_MAJOR_MINOR_SAME(rev1,rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 77 #define MDSS_MDP_REV(major,minor,step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) 78 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) 79 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) 80 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) 81 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) 82 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) 83 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) 84 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) 85 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) 86 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) 87 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) 88 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 89 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) 90 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) 91 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) 92 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) 93 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) 94 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) 95 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) 96 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) 97 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) 98 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) 99 #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) 100 #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) 101 enum { 102 NOTIFY_UPDATE_INIT, 103 NOTIFY_UPDATE_DEINIT, 104 NOTIFY_UPDATE_START, 105 NOTIFY_UPDATE_STOP, 106 NOTIFY_UPDATE_POWER_OFF, 107 }; 108 enum { 109 NOTIFY_TYPE_NO_UPDATE, 110 NOTIFY_TYPE_SUSPEND, 111 NOTIFY_TYPE_UPDATE, 112 NOTIFY_TYPE_BL_UPDATE, 113 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 114 }; 115 enum { 116 MDP_RGB_565, 117 MDP_XRGB_8888, 118 MDP_Y_CBCR_H2V2, 119 MDP_Y_CBCR_H2V2_ADRENO, 120 MDP_ARGB_8888, 121 MDP_RGB_888, 122 MDP_Y_CRCB_H2V2, 123 MDP_YCRYCB_H2V1, 124 MDP_CBYCRY_H2V1, 125 MDP_Y_CRCB_H2V1, 126 MDP_Y_CBCR_H2V1, 127 MDP_Y_CRCB_H1V2, 128 MDP_Y_CBCR_H1V2, 129 MDP_RGBA_8888, 130 MDP_BGRA_8888, 131 MDP_RGBX_8888, 132 MDP_Y_CRCB_H2V2_TILE, 133 MDP_Y_CBCR_H2V2_TILE, 134 MDP_Y_CR_CB_H2V2, 135 MDP_Y_CR_CB_GH2V2, 136 MDP_Y_CB_CR_H2V2, 137 MDP_Y_CRCB_H1V1, 138 MDP_Y_CBCR_H1V1, 139 MDP_YCRCB_H1V1, 140 MDP_YCBCR_H1V1, 141 MDP_BGR_565, 142 MDP_BGR_888, 143 MDP_Y_CBCR_H2V2_VENUS, 144 MDP_BGRX_8888, 145 MDP_RGBA_8888_TILE, 146 MDP_ARGB_8888_TILE, 147 MDP_ABGR_8888_TILE, 148 MDP_BGRA_8888_TILE, 149 MDP_RGBX_8888_TILE, 150 MDP_XRGB_8888_TILE, 151 MDP_XBGR_8888_TILE, 152 MDP_BGRX_8888_TILE, 153 MDP_YCBYCR_H2V1, 154 MDP_RGB_565_TILE, 155 MDP_BGR_565_TILE, 156 MDP_ARGB_1555, 157 MDP_RGBA_5551, 158 MDP_ARGB_4444, 159 MDP_RGBA_4444, 160 MDP_RGB_565_UBWC, 161 MDP_RGBA_8888_UBWC, 162 MDP_Y_CBCR_H2V2_UBWC, 163 MDP_RGBX_8888_UBWC, 164 MDP_Y_CRCB_H2V2_VENUS, 165 MDP_IMGTYPE_LIMIT, 166 MDP_RGB_BORDERFILL, 167 MDP_XRGB_1555, 168 MDP_RGBX_5551, 169 MDP_XRGB_4444, 170 MDP_RGBX_4444, 171 MDP_ABGR_1555, 172 MDP_BGRA_5551, 173 MDP_XBGR_1555, 174 MDP_BGRX_5551, 175 MDP_ABGR_4444, 176 MDP_BGRA_4444, 177 MDP_XBGR_4444, 178 MDP_BGRX_4444, 179 MDP_ABGR_8888, 180 MDP_XBGR_8888, 181 MDP_RGBA_1010102, 182 MDP_ARGB_2101010, 183 MDP_RGBX_1010102, 184 MDP_XRGB_2101010, 185 MDP_BGRA_1010102, 186 MDP_ABGR_2101010, 187 MDP_BGRX_1010102, 188 MDP_XBGR_2101010, 189 MDP_RGBA_1010102_UBWC, 190 MDP_RGBX_1010102_UBWC, 191 MDP_Y_CBCR_H2V2_P010, 192 MDP_Y_CBCR_H2V2_TP10_UBWC, 193 MDP_CRYCBY_H2V1, 194 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 195 MDP_FB_FORMAT = MDP_IMGTYPE2_START, 196 MDP_IMGTYPE_LIMIT2 197 }; 198 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 199 enum { 200 PMEM_IMG, 201 FB_IMG, 202 }; 203 enum { 204 HSIC_HUE = 0, 205 HSIC_SAT, 206 HSIC_INT, 207 HSIC_CON, 208 NUM_HSIC_PARAM, 209 }; 210 enum mdss_mdp_max_bw_mode { 211 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 212 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 213 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 214 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 215 }; 216 #define MDSS_MDP_ROT_ONLY 0x80 217 #define MDSS_MDP_RIGHT_MIXER 0x100 218 #define MDSS_MDP_DUAL_PIPE 0x200 219 #define MDP_ROT_NOP 0 220 #define MDP_FLIP_LR 0x1 221 #define MDP_FLIP_UD 0x2 222 #define MDP_ROT_90 0x4 223 #define MDP_ROT_180 (MDP_FLIP_UD | MDP_FLIP_LR) 224 #define MDP_ROT_270 (MDP_ROT_90 | MDP_FLIP_UD | MDP_FLIP_LR) 225 #define MDP_DITHER 0x8 226 #define MDP_BLUR 0x10 227 #define MDP_BLEND_FG_PREMULT 0x20000 228 #define MDP_IS_FG 0x40000 229 #define MDP_SOLID_FILL 0x00000020 230 #define MDP_VPU_PIPE 0x00000040 231 #define MDP_DEINTERLACE 0x80000000 232 #define MDP_SHARPENING 0x40000000 233 #define MDP_NO_DMA_BARRIER_START 0x20000000 234 #define MDP_NO_DMA_BARRIER_END 0x10000000 235 #define MDP_NO_BLIT 0x08000000 236 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 237 #define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 238 #define MDP_BLIT_SRC_GEM 0x04000000 239 #define MDP_BLIT_DST_GEM 0x02000000 240 #define MDP_BLIT_NON_CACHED 0x01000000 241 #define MDP_OV_PIPE_SHARE 0x00800000 242 #define MDP_DEINTERLACE_ODD 0x00400000 243 #define MDP_OV_PLAY_NOWAIT 0x00200000 244 #define MDP_SOURCE_ROTATED_90 0x00100000 245 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 246 #define MDP_BACKEND_COMPOSITION 0x00040000 247 #define MDP_BORDERFILL_SUPPORTED 0x00010000 248 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 249 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 250 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 251 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 252 #define MDP_BWC_EN 0x00000400 253 #define MDP_DECIMATION_EN 0x00000800 254 #define MDP_SMP_FORCE_ALLOC 0x00200000 255 #define MDP_TRANSP_NOP 0xffffffff 256 #define MDP_ALPHA_NOP 0xff 257 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 258 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 259 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 260 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 261 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 262 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 263 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 264 #define MDP_DEEP_COLOR_YUV444 0x1 265 #define MDP_DEEP_COLOR_RGB30B 0x2 266 #define MDP_DEEP_COLOR_RGB36B 0x4 267 #define MDP_DEEP_COLOR_RGB48B 0x8 268 struct mdp_rect { 269 uint32_t x; 270 uint32_t y; 271 uint32_t w; 272 uint32_t h; 273 }; 274 struct mdp_img { 275 uint32_t width; 276 uint32_t height; 277 uint32_t format; 278 uint32_t offset; 279 int memory_id; 280 uint32_t priv; 281 }; 282 struct mult_factor { 283 uint32_t numer; 284 uint32_t denom; 285 }; 286 #define MDP_CCS_RGB2YUV 0 287 #define MDP_CCS_YUV2RGB 1 288 #define MDP_CCS_SIZE 9 289 #define MDP_BV_SIZE 3 290 struct mdp_ccs { 291 int direction; 292 uint16_t ccs[MDP_CCS_SIZE]; 293 uint16_t bv[MDP_BV_SIZE]; 294 }; 295 struct mdp_csc { 296 int id; 297 uint32_t csc_mv[9]; 298 uint32_t csc_pre_bv[3]; 299 uint32_t csc_post_bv[3]; 300 uint32_t csc_pre_lv[6]; 301 uint32_t csc_post_lv[6]; 302 }; 303 #define MDP_BLIT_REQ_VERSION 3 304 struct color { 305 uint32_t r; 306 uint32_t g; 307 uint32_t b; 308 uint32_t alpha; 309 }; 310 struct mdp_blit_req { 311 struct mdp_img src; 312 struct mdp_img dst; 313 struct mdp_rect src_rect; 314 struct mdp_rect dst_rect; 315 struct color const_color; 316 uint32_t alpha; 317 uint32_t transp_mask; 318 uint32_t flags; 319 int sharpening_strength; 320 uint8_t color_space; 321 uint32_t fps; 322 }; 323 struct mdp_blit_req_list { 324 uint32_t count; 325 struct mdp_blit_req req[]; 326 }; 327 #define MSMFB_DATA_VERSION 2 328 struct msmfb_data { 329 uint32_t offset; 330 int memory_id; 331 int id; 332 uint32_t flags; 333 uint32_t priv; 334 uint32_t iova; 335 }; 336 #define MSMFB_NEW_REQUEST - 1 337 struct msmfb_overlay_data { 338 uint32_t id; 339 struct msmfb_data data; 340 uint32_t version_key; 341 struct msmfb_data plane1_data; 342 struct msmfb_data plane2_data; 343 struct msmfb_data dst_data; 344 }; 345 struct msmfb_img { 346 uint32_t width; 347 uint32_t height; 348 uint32_t format; 349 }; 350 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 351 struct msmfb_writeback_data { 352 struct msmfb_data buf_info; 353 struct msmfb_img img; 354 }; 355 #define MDP_PP_OPS_ENABLE 0x1 356 #define MDP_PP_OPS_READ 0x2 357 #define MDP_PP_OPS_WRITE 0x4 358 #define MDP_PP_OPS_DISABLE 0x8 359 #define MDP_PP_IGC_FLAG_ROM0 0x10 360 #define MDP_PP_IGC_FLAG_ROM1 0x20 361 #define MDSS_PP_DSPP_CFG 0x000 362 #define MDSS_PP_SSPP_CFG 0x100 363 #define MDSS_PP_LM_CFG 0x200 364 #define MDSS_PP_WB_CFG 0x300 365 #define MDSS_PP_ARG_MASK 0x3C00 366 #define MDSS_PP_ARG_NUM 4 367 #define MDSS_PP_ARG_SHIFT 10 368 #define MDSS_PP_LOCATION_MASK 0x0300 369 #define MDSS_PP_LOGICAL_MASK 0x00FF 370 #define MDSS_PP_ADD_ARG(var,arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 371 #define PP_ARG(x,var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 372 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 373 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 374 struct mdp_qseed_cfg { 375 uint32_t table_num; 376 uint32_t ops; 377 uint32_t len; 378 uint32_t * data; 379 }; 380 struct mdp_sharp_cfg { 381 uint32_t flags; 382 uint32_t strength; 383 uint32_t edge_thr; 384 uint32_t smooth_thr; 385 uint32_t noise_thr; 386 }; 387 struct mdp_qseed_cfg_data { 388 uint32_t block; 389 struct mdp_qseed_cfg qseed_data; 390 }; 391 #define MDP_OVERLAY_PP_CSC_CFG 0x1 392 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 393 #define MDP_OVERLAY_PP_PA_CFG 0x4 394 #define MDP_OVERLAY_PP_IGC_CFG 0x8 395 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 396 #define MDP_OVERLAY_PP_HIST_CFG 0x20 397 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 398 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 399 #define MDP_OVERLAY_PP_PCC_CFG 0x100 400 #define MDP_CSC_FLAG_ENABLE 0x1 401 #define MDP_CSC_FLAG_YUV_IN 0x2 402 #define MDP_CSC_FLAG_YUV_OUT 0x4 403 #define MDP_CSC_MATRIX_COEFF_SIZE 9 404 #define MDP_CSC_CLAMP_SIZE 6 405 #define MDP_CSC_BIAS_SIZE 3 406 struct mdp_csc_cfg { 407 uint32_t flags; 408 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 409 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 410 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 411 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 412 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 413 }; 414 struct mdp_csc_cfg_data { 415 uint32_t block; 416 struct mdp_csc_cfg csc_data; 417 }; 418 struct mdp_pa_cfg { 419 uint32_t flags; 420 uint32_t hue_adj; 421 uint32_t sat_adj; 422 uint32_t val_adj; 423 uint32_t cont_adj; 424 }; 425 struct mdp_pa_mem_col_cfg { 426 uint32_t color_adjust_p0; 427 uint32_t color_adjust_p1; 428 uint32_t hue_region; 429 uint32_t sat_region; 430 uint32_t val_region; 431 }; 432 #define MDP_SIX_ZONE_LUT_SIZE 384 433 #define MDP_PP_PA_HUE_ENABLE 0x10 434 #define MDP_PP_PA_SAT_ENABLE 0x20 435 #define MDP_PP_PA_VAL_ENABLE 0x40 436 #define MDP_PP_PA_CONT_ENABLE 0x80 437 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 438 #define MDP_PP_PA_SKIN_ENABLE 0x200 439 #define MDP_PP_PA_SKY_ENABLE 0x400 440 #define MDP_PP_PA_FOL_ENABLE 0x800 441 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 442 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 443 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 444 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 445 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 446 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 447 #define MDP_PP_PA_HUE_MASK 0x1000 448 #define MDP_PP_PA_SAT_MASK 0x2000 449 #define MDP_PP_PA_VAL_MASK 0x4000 450 #define MDP_PP_PA_CONT_MASK 0x8000 451 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 452 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 453 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 454 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 455 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 456 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 457 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 458 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 459 #define MDP_PP_PA_LEFT_HOLD 0x1 460 #define MDP_PP_PA_RIGHT_HOLD 0x2 461 struct mdp_pa_v2_data { 462 uint32_t flags; 463 uint32_t global_hue_adj; 464 uint32_t global_sat_adj; 465 uint32_t global_val_adj; 466 uint32_t global_cont_adj; 467 struct mdp_pa_mem_col_cfg skin_cfg; 468 struct mdp_pa_mem_col_cfg sky_cfg; 469 struct mdp_pa_mem_col_cfg fol_cfg; 470 uint32_t six_zone_len; 471 uint32_t six_zone_thresh; 472 uint32_t * six_zone_curve_p0; 473 uint32_t * six_zone_curve_p1; 474 }; 475 struct mdp_pa_mem_col_data_v1_7 { 476 uint32_t color_adjust_p0; 477 uint32_t color_adjust_p1; 478 uint32_t color_adjust_p2; 479 uint32_t blend_gain; 480 uint8_t sat_hold; 481 uint8_t val_hold; 482 uint32_t hue_region; 483 uint32_t sat_region; 484 uint32_t val_region; 485 }; 486 struct mdp_pa_data_v1_7 { 487 uint32_t mode; 488 uint32_t global_hue_adj; 489 uint32_t global_sat_adj; 490 uint32_t global_val_adj; 491 uint32_t global_cont_adj; 492 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 493 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 494 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 495 uint32_t six_zone_thresh; 496 uint32_t six_zone_adj_p0; 497 uint32_t six_zone_adj_p1; 498 uint8_t six_zone_sat_hold; 499 uint8_t six_zone_val_hold; 500 uint32_t six_zone_len; 501 uint32_t * six_zone_curve_p0; 502 uint32_t * six_zone_curve_p1; 503 }; 504 struct mdp_pa_v2_cfg_data { 505 uint32_t version; 506 uint32_t block; 507 uint32_t flags; 508 struct mdp_pa_v2_data pa_v2_data; 509 void * cfg_payload; 510 }; 511 enum { 512 mdp_igc_rec601 = 1, 513 mdp_igc_rec709, 514 mdp_igc_srgb, 515 mdp_igc_custom, 516 mdp_igc_rec_max, 517 }; 518 struct mdp_igc_lut_data { 519 uint32_t block; 520 uint32_t version; 521 uint32_t len, ops; 522 uint32_t * c0_c1_data; 523 uint32_t * c2_data; 524 void * cfg_payload; 525 }; 526 struct mdp_igc_lut_data_v1_7 { 527 uint32_t table_fmt; 528 uint32_t len; 529 uint32_t * c0_c1_data; 530 uint32_t * c2_data; 531 }; 532 struct mdp_igc_lut_data_payload { 533 uint32_t table_fmt; 534 uint32_t len; 535 uint64_t c0_c1_data; 536 uint64_t c2_data; 537 uint32_t strength; 538 }; 539 struct mdp_histogram_cfg { 540 uint32_t ops; 541 uint32_t block; 542 uint8_t frame_cnt; 543 uint8_t bit_mask; 544 uint16_t num_bins; 545 }; 546 struct mdp_hist_lut_data_v1_7 { 547 uint32_t len; 548 uint32_t * data; 549 }; 550 struct mdp_hist_lut_data { 551 uint32_t block; 552 uint32_t version; 553 uint32_t hist_lut_first; 554 uint32_t ops; 555 uint32_t len; 556 uint32_t * data; 557 void * cfg_payload; 558 }; 559 struct mdp_pcc_coeff { 560 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 561 }; 562 struct mdp_pcc_coeff_v1_7 { 563 uint32_t c, r, g, b, rg, gb, rb, rgb; 564 }; 565 struct mdp_pcc_data_v1_7 { 566 struct mdp_pcc_coeff_v1_7 r, g, b; 567 }; 568 struct mdp_pcc_cfg_data { 569 uint32_t version; 570 uint32_t block; 571 uint32_t ops; 572 struct mdp_pcc_coeff r, g, b; 573 void * cfg_payload; 574 }; 575 enum { 576 mdp_lut_igc, 577 mdp_lut_pgc, 578 mdp_lut_hist, 579 mdp_lut_rgb, 580 mdp_lut_max, 581 }; 582 struct mdp_overlay_pp_params { 583 uint32_t config_ops; 584 struct mdp_csc_cfg csc_cfg; 585 struct mdp_qseed_cfg qseed_cfg[2]; 586 struct mdp_pa_cfg pa_cfg; 587 struct mdp_pa_v2_data pa_v2_cfg; 588 struct mdp_igc_lut_data igc_cfg; 589 struct mdp_sharp_cfg sharp_cfg; 590 struct mdp_histogram_cfg hist_cfg; 591 struct mdp_hist_lut_data hist_lut_cfg; 592 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 593 struct mdp_pcc_cfg_data pcc_cfg_data; 594 }; 595 enum mdss_mdp_blend_op { 596 BLEND_OP_NOT_DEFINED = 0, 597 BLEND_OP_OPAQUE, 598 BLEND_OP_PREMULTIPLIED, 599 BLEND_OP_COVERAGE, 600 BLEND_OP_MAX, 601 }; 602 #define DECIMATED_DIMENSION(dim,deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 603 #define MAX_PLANES 4 604 struct mdp_scale_data { 605 uint8_t enable_pxl_ext; 606 int init_phase_x[MAX_PLANES]; 607 int phase_step_x[MAX_PLANES]; 608 int init_phase_y[MAX_PLANES]; 609 int phase_step_y[MAX_PLANES]; 610 int num_ext_pxls_left[MAX_PLANES]; 611 int num_ext_pxls_right[MAX_PLANES]; 612 int num_ext_pxls_top[MAX_PLANES]; 613 int num_ext_pxls_btm[MAX_PLANES]; 614 int left_ftch[MAX_PLANES]; 615 int left_rpt[MAX_PLANES]; 616 int right_ftch[MAX_PLANES]; 617 int right_rpt[MAX_PLANES]; 618 int top_rpt[MAX_PLANES]; 619 int btm_rpt[MAX_PLANES]; 620 int top_ftch[MAX_PLANES]; 621 int btm_ftch[MAX_PLANES]; 622 uint32_t roi_w[MAX_PLANES]; 623 }; 624 enum mdp_overlay_pipe_type { 625 PIPE_TYPE_AUTO = 0, 626 PIPE_TYPE_VIG, 627 PIPE_TYPE_RGB, 628 PIPE_TYPE_DMA, 629 PIPE_TYPE_CURSOR, 630 PIPE_TYPE_MAX, 631 }; 632 struct mdp_overlay { 633 struct msmfb_img src; 634 struct mdp_rect src_rect; 635 struct mdp_rect dst_rect; 636 uint32_t z_order; 637 uint32_t is_fg; 638 uint32_t alpha; 639 uint32_t blend_op; 640 uint32_t transp_mask; 641 uint32_t flags; 642 uint32_t pipe_type; 643 uint32_t id; 644 uint8_t priority; 645 uint32_t user_data[6]; 646 uint32_t bg_color; 647 uint8_t horz_deci; 648 uint8_t vert_deci; 649 struct mdp_overlay_pp_params overlay_pp_cfg; 650 struct mdp_scale_data scale; 651 uint8_t color_space; 652 uint32_t frame_rate; 653 }; 654 struct msmfb_overlay_3d { 655 uint32_t is_3d; 656 uint32_t width; 657 uint32_t height; 658 }; 659 struct msmfb_overlay_blt { 660 uint32_t enable; 661 uint32_t offset; 662 uint32_t width; 663 uint32_t height; 664 uint32_t bpp; 665 }; 666 struct mdp_histogram { 667 uint32_t frame_cnt; 668 uint32_t bin_cnt; 669 uint32_t * r; 670 uint32_t * g; 671 uint32_t * b; 672 }; 673 #define MISR_CRC_BATCH_SIZE 32 674 enum { 675 DISPLAY_MISR_EDP, 676 DISPLAY_MISR_DSI0, 677 DISPLAY_MISR_DSI1, 678 DISPLAY_MISR_HDMI, 679 DISPLAY_MISR_LCDC, 680 DISPLAY_MISR_MDP, 681 DISPLAY_MISR_ATV, 682 DISPLAY_MISR_DSI_CMD, 683 DISPLAY_MISR_MAX 684 }; 685 enum { 686 MISR_OP_NONE, 687 MISR_OP_SFM, 688 MISR_OP_MFM, 689 MISR_OP_BM, 690 MISR_OP_MAX 691 }; 692 struct mdp_misr { 693 uint32_t block_id; 694 uint32_t frame_count; 695 uint32_t crc_op_mode; 696 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 697 }; 698 enum { 699 MDP_BLOCK_RESERVED = 0, 700 MDP_BLOCK_OVERLAY_0, 701 MDP_BLOCK_OVERLAY_1, 702 MDP_BLOCK_VG_1, 703 MDP_BLOCK_VG_2, 704 MDP_BLOCK_RGB_1, 705 MDP_BLOCK_RGB_2, 706 MDP_BLOCK_DMA_P, 707 MDP_BLOCK_DMA_S, 708 MDP_BLOCK_DMA_E, 709 MDP_BLOCK_OVERLAY_2, 710 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 711 MDP_LOGICAL_BLOCK_DISP_1, 712 MDP_LOGICAL_BLOCK_DISP_2, 713 MDP_BLOCK_MAX, 714 }; 715 struct mdp_histogram_start_req { 716 uint32_t block; 717 uint8_t frame_cnt; 718 uint8_t bit_mask; 719 uint16_t num_bins; 720 }; 721 struct mdp_histogram_data { 722 uint32_t block; 723 uint32_t bin_cnt; 724 uint32_t * c0; 725 uint32_t * c1; 726 uint32_t * c2; 727 uint32_t * extra_info; 728 }; 729 #define GC_LUT_ENTRIES_V1_7 512 730 struct mdp_ar_gc_lut_data { 731 uint32_t x_start; 732 uint32_t slope; 733 uint32_t offset; 734 }; 735 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 736 struct mdp_pgc_lut_data { 737 uint32_t version; 738 uint32_t block; 739 uint32_t flags; 740 uint8_t num_r_stages; 741 uint8_t num_g_stages; 742 uint8_t num_b_stages; 743 struct mdp_ar_gc_lut_data * r_data; 744 struct mdp_ar_gc_lut_data * g_data; 745 struct mdp_ar_gc_lut_data * b_data; 746 void * cfg_payload; 747 }; 748 #define PGC_LUT_ENTRIES 1024 749 struct mdp_pgc_lut_data_v1_7 { 750 uint32_t len; 751 uint32_t * c0_data; 752 uint32_t * c1_data; 753 uint32_t * c2_data; 754 }; 755 struct mdp_rgb_lut_data { 756 uint32_t flags; 757 uint32_t lut_type; 758 struct fb_cmap cmap; 759 }; 760 enum { 761 mdp_rgb_lut_gc, 762 mdp_rgb_lut_hist, 763 }; 764 struct mdp_lut_cfg_data { 765 uint32_t lut_type; 766 union { 767 struct mdp_igc_lut_data igc_lut_data; 768 struct mdp_pgc_lut_data pgc_lut_data; 769 struct mdp_hist_lut_data hist_lut_data; 770 struct mdp_rgb_lut_data rgb_lut_data; 771 } data; 772 }; 773 struct mdp_bl_scale_data { 774 uint32_t min_lvl; 775 uint32_t scale; 776 }; 777 struct mdp_pa_cfg_data { 778 uint32_t block; 779 struct mdp_pa_cfg pa_data; 780 }; 781 #define MDP_DITHER_DATA_V1_7_SZ 16 782 struct mdp_dither_data_v1_7 { 783 uint32_t g_y_depth; 784 uint32_t r_cr_depth; 785 uint32_t b_cb_depth; 786 uint32_t len; 787 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 788 uint32_t temporal_en; 789 }; 790 struct mdp_pa_dither_data { 791 uint64_t data_flags; 792 uint32_t matrix_sz; 793 uint64_t matrix_data; 794 uint32_t strength; 795 uint32_t offset_en; 796 }; 797 struct mdp_dither_cfg_data { 798 uint32_t version; 799 uint32_t block; 800 uint32_t flags; 801 uint32_t mode; 802 uint32_t g_y_depth; 803 uint32_t r_cr_depth; 804 uint32_t b_cb_depth; 805 void * cfg_payload; 806 }; 807 #define MDP_GAMUT_TABLE_NUM 8 808 #define MDP_GAMUT_TABLE_NUM_V1_7 4 809 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 810 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 811 #define MDP_GAMUT_SCALE_OFF_SZ 16 812 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 813 struct mdp_gamut_cfg_data { 814 uint32_t block; 815 uint32_t flags; 816 uint32_t version; 817 uint32_t gamut_first; 818 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 819 uint16_t * r_tbl[MDP_GAMUT_TABLE_NUM]; 820 uint16_t * g_tbl[MDP_GAMUT_TABLE_NUM]; 821 uint16_t * b_tbl[MDP_GAMUT_TABLE_NUM]; 822 void * cfg_payload; 823 }; 824 enum { 825 mdp_gamut_fine_mode = 0x1, 826 mdp_gamut_coarse_mode, 827 }; 828 struct mdp_gamut_data_v1_7 { 829 uint32_t mode; 830 uint32_t map_en; 831 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 832 uint32_t * c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 833 uint32_t * c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 834 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 835 uint32_t * scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 836 }; 837 struct mdp_calib_config_data { 838 uint32_t ops; 839 uint32_t addr; 840 uint32_t data; 841 }; 842 struct mdp_calib_config_buffer { 843 uint32_t ops; 844 uint32_t size; 845 uint32_t * buffer; 846 }; 847 struct mdp_calib_dcm_state { 848 uint32_t ops; 849 uint32_t dcm_state; 850 }; 851 enum { 852 DCM_UNINIT, 853 DCM_UNBLANK, 854 DCM_ENTER, 855 DCM_EXIT, 856 DCM_BLANK, 857 DTM_ENTER, 858 DTM_EXIT, 859 }; 860 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 861 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 862 #define MDSS_PP_SPLIT_MASK 0x30000000 863 #define MDSS_MAX_BL_BRIGHTNESS 255 864 #define AD_BL_LIN_LEN 256 865 #define AD_BL_ATT_LUT_LEN 33 866 #define MDSS_AD_MODE_AUTO_BL 0x0 867 #define MDSS_AD_MODE_AUTO_STR 0x1 868 #define MDSS_AD_MODE_TARG_STR 0x3 869 #define MDSS_AD_MODE_MAN_STR 0x7 870 #define MDSS_AD_MODE_CALIB 0xF 871 #define MDP_PP_AD_INIT 0x10 872 #define MDP_PP_AD_CFG 0x20 873 struct mdss_ad_init { 874 uint32_t asym_lut[33]; 875 uint32_t color_corr_lut[33]; 876 uint8_t i_control[2]; 877 uint16_t black_lvl; 878 uint16_t white_lvl; 879 uint8_t var; 880 uint8_t limit_ampl; 881 uint8_t i_dither; 882 uint8_t slope_max; 883 uint8_t slope_min; 884 uint8_t dither_ctl; 885 uint8_t format; 886 uint8_t auto_size; 887 uint16_t frame_w; 888 uint16_t frame_h; 889 uint8_t logo_v; 890 uint8_t logo_h; 891 uint32_t alpha; 892 uint32_t alpha_base; 893 uint32_t al_thresh; 894 uint32_t bl_lin_len; 895 uint32_t bl_att_len; 896 uint32_t * bl_lin; 897 uint32_t * bl_lin_inv; 898 uint32_t * bl_att_lut; 899 }; 900 #define MDSS_AD_BL_CTRL_MODE_EN 1 901 #define MDSS_AD_BL_CTRL_MODE_DIS 0 902 struct mdss_ad_cfg { 903 uint32_t mode; 904 uint32_t al_calib_lut[33]; 905 uint16_t backlight_min; 906 uint16_t backlight_max; 907 uint16_t backlight_scale; 908 uint16_t amb_light_min; 909 uint16_t filter[2]; 910 uint16_t calib[4]; 911 uint8_t strength_limit; 912 uint8_t t_filter_recursion; 913 uint16_t stab_itr; 914 uint32_t bl_ctrl_mode; 915 }; 916 struct mdss_ad_bl_cfg { 917 uint32_t bl_min_delta; 918 uint32_t bl_low_limit; 919 }; 920 struct mdss_ad_init_cfg { 921 uint32_t ops; 922 union { 923 struct mdss_ad_init init; 924 struct mdss_ad_cfg cfg; 925 } params; 926 }; 927 struct mdss_ad_input { 928 uint32_t mode; 929 union { 930 uint32_t amb_light; 931 uint32_t strength; 932 uint32_t calib_bl; 933 } in; 934 uint32_t output; 935 }; 936 #define MDSS_CALIB_MODE_BL 0x1 937 struct mdss_calib_cfg { 938 uint32_t ops; 939 uint32_t calib_mask; 940 }; 941 enum { 942 mdp_op_pcc_cfg, 943 mdp_op_csc_cfg, 944 mdp_op_lut_cfg, 945 mdp_op_qseed_cfg, 946 mdp_bl_scale_cfg, 947 mdp_op_pa_cfg, 948 mdp_op_pa_v2_cfg, 949 mdp_op_dither_cfg, 950 mdp_op_gamut_cfg, 951 mdp_op_calib_cfg, 952 mdp_op_ad_cfg, 953 mdp_op_ad_input, 954 mdp_op_calib_mode, 955 mdp_op_calib_buffer, 956 mdp_op_calib_dcm_state, 957 mdp_op_max, 958 mdp_op_pa_dither_cfg, 959 mdp_op_ad_bl_cfg, 960 mdp_op_pp_max = 255, 961 }; 962 #define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg 963 #define mdp_op_pp_max mdp_op_pp_max 964 #define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg 965 enum { 966 WB_FORMAT_NV12, 967 WB_FORMAT_RGB_565, 968 WB_FORMAT_RGB_888, 969 WB_FORMAT_xRGB_8888, 970 WB_FORMAT_ARGB_8888, 971 WB_FORMAT_BGRA_8888, 972 WB_FORMAT_BGRX_8888, 973 WB_FORMAT_ARGB_8888_INPUT_ALPHA 974 }; 975 struct msmfb_mdp_pp { 976 uint32_t op; 977 union { 978 struct mdp_pcc_cfg_data pcc_cfg_data; 979 struct mdp_csc_cfg_data csc_cfg_data; 980 struct mdp_lut_cfg_data lut_cfg_data; 981 struct mdp_qseed_cfg_data qseed_cfg_data; 982 struct mdp_bl_scale_data bl_scale_data; 983 struct mdp_pa_cfg_data pa_cfg_data; 984 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 985 struct mdp_dither_cfg_data dither_cfg_data; 986 struct mdp_gamut_cfg_data gamut_cfg_data; 987 struct mdp_calib_config_data calib_cfg; 988 struct mdss_ad_init_cfg ad_init_cfg; 989 struct mdss_calib_cfg mdss_calib_cfg; 990 struct mdss_ad_input ad_input; 991 struct mdp_calib_config_buffer calib_buffer; 992 struct mdp_calib_dcm_state calib_dcm; 993 struct mdss_ad_bl_cfg ad_bl_cfg; 994 } data; 995 }; 996 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 997 enum { 998 metadata_op_none, 999 metadata_op_base_blend, 1000 metadata_op_frame_rate, 1001 metadata_op_vic, 1002 metadata_op_wb_format, 1003 metadata_op_wb_secure, 1004 metadata_op_get_caps, 1005 metadata_op_crc, 1006 metadata_op_get_ion_fd, 1007 metadata_op_max 1008 }; 1009 struct mdp_blend_cfg { 1010 uint32_t is_premultiplied; 1011 }; 1012 struct mdp_mixer_cfg { 1013 uint32_t writeback_format; 1014 uint32_t alpha; 1015 }; 1016 struct mdss_hw_caps { 1017 uint32_t mdp_rev; 1018 uint8_t rgb_pipes; 1019 uint8_t vig_pipes; 1020 uint8_t dma_pipes; 1021 uint8_t max_smp_cnt; 1022 uint8_t smp_per_pipe; 1023 uint32_t features; 1024 }; 1025 struct msmfb_metadata { 1026 uint32_t op; 1027 uint32_t flags; 1028 union { 1029 struct mdp_misr misr_request; 1030 struct mdp_blend_cfg blend_cfg; 1031 struct mdp_mixer_cfg mixer_cfg; 1032 uint32_t panel_frame_rate; 1033 uint32_t video_info_code; 1034 struct mdss_hw_caps caps; 1035 uint8_t secure_en; 1036 int fbmem_ionfd; 1037 } data; 1038 }; 1039 #define MDP_MAX_FENCE_FD 32 1040 #define MDP_BUF_SYNC_FLAG_WAIT 1 1041 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1042 struct mdp_buf_sync { 1043 uint32_t flags; 1044 uint32_t acq_fen_fd_cnt; 1045 uint32_t session_id; 1046 int * acq_fen_fd; 1047 int * rel_fen_fd; 1048 int * retire_fen_fd; 1049 }; 1050 struct mdp_async_blit_req_list { 1051 struct mdp_buf_sync sync; 1052 uint32_t count; 1053 struct mdp_blit_req req[]; 1054 }; 1055 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1056 struct mdp_display_commit { 1057 uint32_t flags; 1058 uint32_t wait_for_finish; 1059 struct fb_var_screeninfo var; 1060 struct mdp_rect l_roi; 1061 struct mdp_rect r_roi; 1062 }; 1063 struct mdp_overlay_list { 1064 uint32_t num_overlays; 1065 struct mdp_overlay * * overlay_list; 1066 uint32_t flags; 1067 uint32_t processed_overlays; 1068 }; 1069 struct mdp_page_protection { 1070 uint32_t page_protection; 1071 }; 1072 struct mdp_mixer_info { 1073 int pndx; 1074 int pnum; 1075 int ptype; 1076 int mixer_num; 1077 int z_order; 1078 }; 1079 #define MAX_PIPE_PER_MIXER 7 1080 struct msmfb_mixer_info_req { 1081 int mixer_num; 1082 int cnt; 1083 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1084 }; 1085 enum { 1086 DISPLAY_SUBSYSTEM_ID, 1087 ROTATOR_SUBSYSTEM_ID, 1088 }; 1089 enum { 1090 MDP_IOMMU_DOMAIN_CP, 1091 MDP_IOMMU_DOMAIN_NS, 1092 }; 1093 enum { 1094 MDP_WRITEBACK_MIRROR_OFF, 1095 MDP_WRITEBACK_MIRROR_ON, 1096 MDP_WRITEBACK_MIRROR_PAUSE, 1097 MDP_WRITEBACK_MIRROR_RESUME, 1098 }; 1099 enum mdp_color_space { 1100 MDP_CSC_ITU_R_601, 1101 MDP_CSC_ITU_R_601_FR, 1102 MDP_CSC_ITU_R_709, 1103 }; 1104 #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1105 #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1106 enum { 1107 mdp_igc_v1_7 = 1, 1108 mdp_igc_vmax, 1109 mdp_hist_lut_v1_7, 1110 mdp_hist_lut_vmax, 1111 mdp_pgc_v1_7, 1112 mdp_pgc_vmax, 1113 mdp_dither_v1_7, 1114 mdp_dither_vmax, 1115 mdp_gamut_v1_7, 1116 mdp_gamut_vmax, 1117 mdp_pa_v1_7, 1118 mdp_pa_vmax, 1119 mdp_pcc_v1_7, 1120 mdp_pcc_vmax, 1121 mdp_pp_legacy, 1122 mdp_dither_pa_v1_7, 1123 mdp_igc_v3, 1124 mdp_pp_unknown = 255 1125 }; 1126 #define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 1127 #define mdp_pp_unknown mdp_pp_unknown 1128 #define mdp_igc_v3 mdp_igc_v3 1129 enum { 1130 IGC = 1, 1131 PCC, 1132 GC, 1133 PA, 1134 GAMUT, 1135 DITHER, 1136 QSEED, 1137 HIST_LUT, 1138 HIST, 1139 PP_FEATURE_MAX, 1140 PA_DITHER, 1141 PP_MAX_FEATURES = 25, 1142 }; 1143 #define PA_DITHER PA_DITHER 1144 #define PP_MAX_FEATURES PP_MAX_FEATURES 1145 struct mdp_pp_feature_version { 1146 uint32_t pp_feature; 1147 uint32_t version_info; 1148 }; 1149 #endif 1150 1151