1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __UAPI_LINUX_CAM_REQ_MGR_H 20 #define __UAPI_LINUX_CAM_REQ_MGR_H 21 #include <linux/videodev2.h> 22 #include <linux/types.h> 23 #include <linux/ioctl.h> 24 #include <linux/media.h> 25 #include <media/cam_defs.h> 26 #define CAM_REQ_MGR_VNODE_NAME "cam-req-mgr-devnode" 27 #define CAM_DEVICE_TYPE_BASE (MEDIA_ENT_F_OLD_BASE) 28 #define CAM_VNODE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE) 29 #define CAM_SENSOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 1) 30 #define CAM_IFE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 2) 31 #define CAM_ICP_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 3) 32 #define CAM_LRME_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 4) 33 #define CAM_JPEG_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 5) 34 #define CAM_FD_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 6) 35 #define CAM_CPAS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 7) 36 #define CAM_CSIPHY_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 8) 37 #define CAM_ACTUATOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 9) 38 #define CAM_CCI_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 10) 39 #define CAM_FLASH_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 11) 40 #define CAM_EEPROM_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 12) 41 #define CAM_OIS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 13) 42 #define CAM_REQ_MGR_HDL_IDX_POS 8 43 #define CAM_REQ_MGR_HDL_IDX_MASK ((1 << CAM_REQ_MGR_HDL_IDX_POS) - 1) 44 #define CAM_REQ_MGR_GET_HDL_IDX(hdl) (hdl & CAM_REQ_MGR_HDL_IDX_MASK) 45 #define CAM_REQ_MGR_MAX_HANDLES 64 46 #define MAX_LINKS_PER_SESSION 2 47 #define V4L_EVENT_CAM_REQ_MGR_EVENT (V4L2_EVENT_PRIVATE_START + 0) 48 #define V4L_EVENT_CAM_REQ_MGR_SOF 0 49 #define V4L_EVENT_CAM_REQ_MGR_ERROR 1 50 #define V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS 2 51 #define V4L_EVENT_CAM_REQ_MGR_MAX 3 52 #define CAM_REQ_MGR_SOF_EVENT_SUCCESS 0 53 #define CAM_REQ_MGR_SOF_EVENT_ERROR 1 54 #define CAM_REQ_MGR_LINK_ACTIVATE 0 55 #define CAM_REQ_MGR_LINK_DEACTIVATE 1 56 #define CAM_REQ_MGR_FLUSH_TYPE_ALL 0 57 #define CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ 1 58 #define CAM_REQ_MGR_FLUSH_TYPE_MAX 2 59 #define CAM_REQ_MGR_SYNC_MODE_NO_SYNC 0 60 #define CAM_REQ_MGR_SYNC_MODE_SYNC 1 61 struct cam_req_mgr_event_data { 62 int32_t session_hdl; 63 int32_t link_hdl; 64 int32_t frame_id; 65 int32_t reserved; 66 int64_t req_id; 67 uint64_t tv_sec; 68 uint64_t tv_usec; 69 }; 70 struct cam_req_mgr_session_info { 71 int32_t session_hdl; 72 int32_t reserved; 73 }; 74 struct cam_req_mgr_link_info { 75 int32_t session_hdl; 76 uint32_t num_devices; 77 int32_t dev_hdls[CAM_REQ_MGR_MAX_HANDLES]; 78 int32_t link_hdl; 79 }; 80 struct cam_req_mgr_unlink_info { 81 int32_t session_hdl; 82 int32_t link_hdl; 83 }; 84 struct cam_req_mgr_flush_info { 85 int32_t session_hdl; 86 int32_t link_hdl; 87 uint32_t flush_type; 88 uint32_t reserved; 89 int64_t req_id; 90 }; 91 struct cam_req_mgr_sched_request { 92 int32_t session_hdl; 93 int32_t link_hdl; 94 int32_t bubble_enable; 95 int32_t sync_mode; 96 int64_t req_id; 97 }; 98 struct cam_req_mgr_sync_mode { 99 int32_t session_hdl; 100 int32_t sync_mode; 101 int32_t num_links; 102 int32_t link_hdls[MAX_LINKS_PER_SESSION]; 103 int32_t master_link_hdl; 104 int32_t reserved; 105 }; 106 struct cam_req_mgr_link_control { 107 int32_t ops; 108 int32_t session_hdl; 109 int32_t num_links; 110 int32_t reserved; 111 int32_t link_hdls[MAX_LINKS_PER_SESSION]; 112 }; 113 #define CAM_REQ_MGR_CREATE_DEV_NODES (CAM_COMMON_OPCODE_MAX + 1) 114 #define CAM_REQ_MGR_CREATE_SESSION (CAM_COMMON_OPCODE_MAX + 2) 115 #define CAM_REQ_MGR_DESTROY_SESSION (CAM_COMMON_OPCODE_MAX + 3) 116 #define CAM_REQ_MGR_LINK (CAM_COMMON_OPCODE_MAX + 4) 117 #define CAM_REQ_MGR_UNLINK (CAM_COMMON_OPCODE_MAX + 5) 118 #define CAM_REQ_MGR_SCHED_REQ (CAM_COMMON_OPCODE_MAX + 6) 119 #define CAM_REQ_MGR_FLUSH_REQ (CAM_COMMON_OPCODE_MAX + 7) 120 #define CAM_REQ_MGR_SYNC_MODE (CAM_COMMON_OPCODE_MAX + 8) 121 #define CAM_REQ_MGR_ALLOC_BUF (CAM_COMMON_OPCODE_MAX + 9) 122 #define CAM_REQ_MGR_MAP_BUF (CAM_COMMON_OPCODE_MAX + 10) 123 #define CAM_REQ_MGR_RELEASE_BUF (CAM_COMMON_OPCODE_MAX + 11) 124 #define CAM_REQ_MGR_CACHE_OPS (CAM_COMMON_OPCODE_MAX + 12) 125 #define CAM_REQ_MGR_LINK_CONTROL (CAM_COMMON_OPCODE_MAX + 13) 126 #define CAM_MEM_FLAG_HW_READ_WRITE (1 << 0) 127 #define CAM_MEM_FLAG_HW_READ_ONLY (1 << 1) 128 #define CAM_MEM_FLAG_HW_WRITE_ONLY (1 << 2) 129 #define CAM_MEM_FLAG_KMD_ACCESS (1 << 3) 130 #define CAM_MEM_FLAG_UMD_ACCESS (1 << 4) 131 #define CAM_MEM_FLAG_PROTECTED_MODE (1 << 5) 132 #define CAM_MEM_FLAG_CMD_BUF_TYPE (1 << 6) 133 #define CAM_MEM_FLAG_PIXEL_BUF_TYPE (1 << 7) 134 #define CAM_MEM_FLAG_STATS_BUF_TYPE (1 << 8) 135 #define CAM_MEM_FLAG_PACKET_BUF_TYPE (1 << 9) 136 #define CAM_MEM_FLAG_CACHE (1 << 10) 137 #define CAM_MEM_FLAG_HW_SHARED_ACCESS (1 << 11) 138 #define CAM_MEM_MMU_MAX_HANDLE 16 139 #define CAM_MEM_BUFQ_MAX 1024 140 #define CAM_MEM_MGR_SECURE_BIT_POS 15 141 #define CAM_MEM_MGR_HDL_IDX_SIZE 15 142 #define CAM_MEM_MGR_HDL_FD_SIZE 16 143 #define CAM_MEM_MGR_HDL_IDX_END_POS 16 144 #define CAM_MEM_MGR_HDL_FD_END_POS 32 145 #define CAM_MEM_MGR_HDL_IDX_MASK ((1 << CAM_MEM_MGR_HDL_IDX_SIZE) - 1) 146 #define GET_MEM_HANDLE(idx,fd) ((idx & CAM_MEM_MGR_HDL_IDX_MASK) | (fd << (CAM_MEM_MGR_HDL_FD_END_POS - CAM_MEM_MGR_HDL_FD_SIZE))) 147 #define CAM_MEM_MGR_GET_HDL_IDX(hdl) (hdl & CAM_MEM_MGR_HDL_IDX_MASK) 148 #define CAM_MEM_MGR_SET_SECURE_HDL(hdl,flag) ((flag) ? (hdl |= (1 << CAM_MEM_MGR_SECURE_BIT_POS)) : ((hdl) &= ~(1 << CAM_MEM_MGR_SECURE_BIT_POS))) 149 #define CAM_MEM_MGR_IS_SECURE_HDL(hdl) (((hdl) & (1 << CAM_MEM_MGR_SECURE_BIT_POS)) >> CAM_MEM_MGR_SECURE_BIT_POS) 150 #define CAM_MEM_DMA_NONE 0 151 #define CAM_MEM_DMA_BIDIRECTIONAL 1 152 #define CAM_MEM_DMA_TO_DEVICE 2 153 #define CAM_MEM_DMA_FROM_DEVICE 3 154 #define CAM_MEM_CLEAN_CACHE 1 155 #define CAM_MEM_INV_CACHE 2 156 #define CAM_MEM_CLEAN_INV_CACHE 3 157 struct cam_mem_alloc_out_params { 158 uint32_t buf_handle; 159 int32_t fd; 160 uint64_t vaddr; 161 }; 162 struct cam_mem_map_out_params { 163 uint32_t buf_handle; 164 uint32_t reserved; 165 uint64_t vaddr; 166 }; 167 struct cam_mem_mgr_alloc_cmd { 168 uint64_t len; 169 uint64_t align; 170 int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE]; 171 uint32_t num_hdl; 172 uint32_t flags; 173 struct cam_mem_alloc_out_params out; 174 }; 175 struct cam_mem_mgr_map_cmd { 176 int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE]; 177 uint32_t num_hdl; 178 uint32_t flags; 179 int32_t fd; 180 uint32_t reserved; 181 struct cam_mem_map_out_params out; 182 }; 183 struct cam_mem_mgr_release_cmd { 184 int32_t buf_handle; 185 uint32_t reserved; 186 }; 187 struct cam_mem_cache_ops_cmd { 188 int32_t buf_handle; 189 uint32_t mem_cache_ops; 190 }; 191 #define CAM_REQ_MGR_ERROR_TYPE_DEVICE 0 192 #define CAM_REQ_MGR_ERROR_TYPE_REQUEST 1 193 #define CAM_REQ_MGR_ERROR_TYPE_BUFFER 2 194 struct cam_req_mgr_error_msg { 195 uint32_t error_type; 196 uint32_t request_id; 197 int32_t device_hdl; 198 int32_t link_hdl; 199 uint64_t resource_size; 200 }; 201 struct cam_req_mgr_frame_msg { 202 uint64_t request_id; 203 uint64_t frame_id; 204 uint64_t timestamp; 205 int32_t link_hdl; 206 uint32_t sof_status; 207 }; 208 struct cam_req_mgr_message { 209 int32_t session_hdl; 210 int32_t reserved; 211 union { 212 struct cam_req_mgr_error_msg err_msg; 213 struct cam_req_mgr_frame_msg frame_msg; 214 } u; 215 }; 216 #endif 217 218