1 /****************************************************************************
2  ****************************************************************************
3  ***
4  ***   This header was automatically generated from a Linux kernel header
5  ***   of the same name, to make information necessary for userspace to
6  ***   call into the kernel available to libc.  It contains only constants,
7  ***   structures, and macros generated from the original header, and thus,
8  ***   contains no copyrightable information.
9  ***
10  ***   To edit the content of this header, modify the corresponding
11  ***   source file (e.g. under external/kernel-headers/original/) then
12  ***   run bionic/libc/kernel/tools/update_all.py
13  ***
14  ***   Any manual change here will be lost the next time this script will
15  ***   be run. You've been warned!
16  ***
17  ****************************************************************************
18  ****************************************************************************/
19 #ifndef _H_MSM_VPU_H_
20 #define _H_MSM_VPU_H_
21 #include <linux/videodev2.h>
22 #define V4L2_BUF_FLAG_CDS_ENABLE 0x10000000
23 #define V4L2_PLANE_MEM_OFFSET 0
24 enum vpu_colorspace {
25   VPU_CS_MIN = 0,
26   VPU_CS_RGB_FULL = 1,
27   VPU_CS_RGB_LIMITED = 2,
28   VPU_CS_REC601_FULL = 3,
29   VPU_CS_REC601_LIMITED = 4,
30   VPU_CS_REC709_FULL = 5,
31   VPU_CS_REC709_LIMITED = 6,
32   VPU_CS_SMPTE240_FULL = 7,
33   VPU_CS_SMPTE240_LIMITED = 8,
34   VPU_CS_MAX = 9,
35 };
36 #define VPU_FMT_EXT_FLAG_BT 1
37 #define VPU_FMT_EXT_FLAG_TB 2
38 #define VPU_FMT_EXT_FLAG_3D 4
39 struct v4l2_format_vpu_extension {
40   __u8 flag;
41   __u8 gap_in_lines;
42 };
43 #define V4L2_PIX_FMT_XRGB2 v4l2_fourcc('X', 'R', 'G', '2')
44 #define V4L2_PIX_FMT_XBGR2 v4l2_fourcc('X', 'B', 'G', '2')
45 #define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'L')
46 #define V4L2_PIX_FMT_YUV8 v4l2_fourcc('Y', 'U', 'V', '8')
47 #define V4L2_PIX_FMT_YUV10 v4l2_fourcc('Y', 'U', 'V', 'L')
48 #define V4L2_PIX_FMT_YUYV10BWC v4l2_fourcc('Y', 'B', 'W', 'C')
49 #define VPU_INPUT_TYPE_HOST 0
50 #define VPU_INPUT_TYPE_VCAP 1
51 #define VPU_OUTPUT_TYPE_HOST 0
52 #define VPU_OUTPUT_TYPE_DISPLAY 1
53 #define VPU_PIPE_VCAP0 (1 << 16)
54 #define VPU_PIPE_VCAP1 (1 << 17)
55 #define VPU_PIPE_DISPLAY0 (1 << 18)
56 #define VPU_PIPE_DISPLAY1 (1 << 19)
57 #define VPU_PIPE_DISPLAY2 (1 << 20)
58 #define VPU_PIPE_DISPLAY3 (1 << 21)
59 #define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000)
60 enum VPU_PRIVATE_EVENT {
61   VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE,
62   VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1,
63   VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2,
64   VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3,
65   VPU_EVENT_SESSION_CREATED = VPU_EVENT_START + 4,
66   VPU_EVENT_SESSION_FREED = VPU_EVENT_START + 5,
67   VPU_EVENT_SESSION_CLIENT_EXITED = VPU_EVENT_START + 6,
68   VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11,
69   VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12,
70   VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13,
71   VPU_EVENT_END
72 };
73 struct vpu_ctrl_standard {
74   __u32 enable;
75   __s32 value;
76 };
77 struct vpu_ctrl_auto_manual {
78   __u32 enable;
79   __u32 auto_mode;
80   __s32 value;
81 };
82 struct vpu_ctrl_range_mapping {
83   __u32 enable;
84   __u32 y_range;
85   __u32 uv_range;
86 };
87 #define VPU_ACTIVE_REGION_N_EXCLUSIONS 1
88 struct vpu_ctrl_active_region_param {
89   __u32 enable;
90   __u32 num_exclusions;
91   struct v4l2_rect detection_region;
92   struct v4l2_rect excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS];
93 };
94 struct vpu_ctrl_deinterlacing_mode {
95   __u32 field_polarity;
96   __u32 mvp_mode;
97 };
98 struct vpu_ctrl_hqv {
99   __u32 enable;
100   __u32 sharpen_strength;
101   __u32 auto_nr_strength;
102 };
103 struct vpu_info_frame_timestamp {
104   __u32 pts_low;
105   __u32 pts_high;
106   __u32 qtime_low;
107   __u32 qtime_high;
108 };
109 struct vpu_control {
110   __u32 control_id;
111   union control_data {
112     __s32 value;
113     struct vpu_ctrl_standard standard;
114     struct vpu_ctrl_auto_manual auto_manual;
115     struct vpu_ctrl_range_mapping range_mapping;
116     struct vpu_ctrl_active_region_param active_region_param;
117     struct v4l2_rect active_region_result;
118     struct vpu_ctrl_deinterlacing_mode deinterlacing_mode;
119     struct vpu_ctrl_hqv hqv;
120     struct vpu_info_frame_timestamp timestamp;
121     __u8 reserved[124];
122   } data;
123 };
124 #define VPU_CTRL_ID_MIN 0
125 #define VPU_CTRL_NOISE_REDUCTION 1
126 #define VPU_CTRL_IMAGE_ENHANCEMENT 2
127 #define VPU_CTRL_ANAMORPHIC_SCALING 3
128 #define VPU_CTRL_DIRECTIONAL_INTERPOLATION 4
129 #define VPU_CTRL_BACKGROUND_COLOR 5
130 #define VPU_CTRL_RANGE_MAPPING 6
131 #define VPU_CTRL_DEINTERLACING_MODE 7
132 #define VPU_CTRL_ACTIVE_REGION_PARAM 8
133 #define VPU_CTRL_ACTIVE_REGION_RESULT 9
134 #define VPU_CTRL_PRIORITY 10
135 #define VPU_CTRL_CONTENT_PROTECTION 11
136 #define VPU_CTRL_DISPLAY_REFRESH_RATE 12
137 #define VPU_CTRL_HQV 20
138 #define VPU_CTRL_HQV_SHARPEN 21
139 #define VPU_CTRL_HQV_AUTONR 22
140 #define VPU_CTRL_ACE 23
141 #define VPU_CTRL_ACE_BRIGHTNESS 24
142 #define VPU_CTRL_ACE_CONTRAST 25
143 #define VPU_CTRL_2D3D 26
144 #define VPU_CTRL_2D3D_DEPTH 27
145 #define VPU_CTRL_FRC 28
146 #define VPU_CTRL_FRC_MOTION_SMOOTHNESS 29
147 #define VPU_CTRL_FRC_MOTION_CLEAR 30
148 #define VPU_INFO_TIMESTAMP 35
149 #define VPU_CTRL_TIMESTAMP_INFO_MODE 36
150 #define VPU_INFO_STATISTICS 37
151 #define VPU_CTRL_LATENCY 38
152 #define VPU_CTRL_LATENCY_MODE 39
153 #define VPU_CTRL_ID_MAX 40
154 #define VPU_MAX_EXT_DATA_SIZE 720
155 struct vpu_control_extended {
156   __u32 type;
157   __u32 data_len;
158   void * data_ptr;
159   __u32 buf_size;
160   void * buf_ptr;
161 };
162 struct vpu_control_port {
163   __u32 control_id;
164   __u32 port;
165   union control_port_data {
166     __u32 framerate;
167   } data;
168 };
169 #define VPU_CTRL_FPS 1000
170 #define VPU_ATTACH_TO_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 1), int)
171 #define VPU_QUERY_SESSIONS _IOR('V', (BASE_VIDIOC_PRIVATE + 0), int)
172 #define VPU_CREATE_SESSION _IOR('V', (BASE_VIDIOC_PRIVATE + 2), int)
173 #define VPU_JOIN_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 3), int)
174 #define VPU_CREATE_OUTPUT2 _IO('V', (BASE_VIDIOC_PRIVATE + 5))
175 #define VPU_COMMIT_CONFIGURATION _IO('V', (BASE_VIDIOC_PRIVATE + 10))
176 #define VPU_FLUSH_BUFS _IOW('V', (BASE_VIDIOC_PRIVATE + 15), enum v4l2_buf_type)
177 #define VPU_G_CONTROL _IOWR('V', (BASE_VIDIOC_PRIVATE + 20), struct vpu_control)
178 #define VPU_S_CONTROL _IOW('V', (BASE_VIDIOC_PRIVATE + 21), struct vpu_control)
179 #define VPU_G_CONTROL_EXTENDED _IOWR('V', (BASE_VIDIOC_PRIVATE + 22), struct vpu_control_extended)
180 #define VPU_S_CONTROL_EXTENDED _IOW('V', (BASE_VIDIOC_PRIVATE + 23), struct vpu_control_extended)
181 #define VPU_G_CONTROL_PORT _IOWR('V', (BASE_VIDIOC_PRIVATE + 24), struct vpu_control_port)
182 #define VPU_S_CONTROL_PORT _IOW('V', (BASE_VIDIOC_PRIVATE + 25), struct vpu_control_port)
183 #endif
184 
185