1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __UAPI_MSMB_ISP__ 20 #define __UAPI_MSMB_ISP__ 21 #include <linux/videodev2.h> 22 #include <media/msmb_camera.h> 23 #define MAX_PLANES_PER_STREAM 3 24 #define MAX_NUM_STREAM 7 25 #define ISP_VERSION_48 48 26 #define ISP_VERSION_47 47 27 #define ISP_VERSION_46 46 28 #define ISP_VERSION_44 44 29 #define ISP_VERSION_40 40 30 #define ISP_VERSION_32 32 31 #define ISP_NATIVE_BUF_BIT (0x10000 << 0) 32 #define ISP0_BIT (0x10000 << 1) 33 #define ISP1_BIT (0x10000 << 2) 34 #define ISP_META_CHANNEL_BIT (0x10000 << 3) 35 #define ISP_SCRATCH_BUF_BIT (0x10000 << 4) 36 #define ISP_OFFLINE_STATS_BIT (0x10000 << 5) 37 #define ISP_SVHDR_IN_BIT (0x10000 << 6) 38 #define ISP_SVHDR_OUT_BIT (0x10000 << 7) 39 #define ISP_STATS_STREAM_BIT 0x80000000 40 #define VFE_HW_LIMIT 1 41 struct msm_vfe_cfg_cmd_list; 42 enum ISP_START_PIXEL_PATTERN { 43 ISP_BAYER_RGRGRG, 44 ISP_BAYER_GRGRGR, 45 ISP_BAYER_BGBGBG, 46 ISP_BAYER_GBGBGB, 47 ISP_YUV_YCbYCr, 48 ISP_YUV_YCrYCb, 49 ISP_YUV_CbYCrY, 50 ISP_YUV_CrYCbY, 51 ISP_PIX_PATTERN_MAX 52 }; 53 enum msm_vfe_plane_fmt { 54 Y_PLANE, 55 CB_PLANE, 56 CR_PLANE, 57 CRCB_PLANE, 58 CBCR_PLANE, 59 VFE_PLANE_FMT_MAX 60 }; 61 enum msm_vfe_input_src { 62 VFE_PIX_0, 63 VFE_RAW_0, 64 VFE_RAW_1, 65 VFE_RAW_2, 66 VFE_SRC_MAX, 67 }; 68 enum msm_vfe_axi_stream_src { 69 PIX_ENCODER, 70 PIX_VIEWFINDER, 71 PIX_VIDEO, 72 CAMIF_RAW, 73 IDEAL_RAW, 74 RDI_INTF_0, 75 RDI_INTF_1, 76 RDI_INTF_2, 77 VFE_AXI_SRC_MAX 78 }; 79 enum msm_vfe_frame_skip_pattern { 80 NO_SKIP, 81 EVERY_2FRAME, 82 EVERY_3FRAME, 83 EVERY_4FRAME, 84 EVERY_5FRAME, 85 EVERY_6FRAME, 86 EVERY_7FRAME, 87 EVERY_8FRAME, 88 EVERY_16FRAME, 89 EVERY_32FRAME, 90 SKIP_ALL, 91 SKIP_RANGE, 92 MAX_SKIP, 93 }; 94 #define MSM_VFE_STREAM_STOP_PERIOD 15 95 enum msm_isp_stats_type { 96 MSM_ISP_STATS_AEC, 97 MSM_ISP_STATS_AF, 98 MSM_ISP_STATS_AWB, 99 MSM_ISP_STATS_RS, 100 MSM_ISP_STATS_CS, 101 MSM_ISP_STATS_IHIST, 102 MSM_ISP_STATS_SKIN, 103 MSM_ISP_STATS_BG, 104 MSM_ISP_STATS_BF, 105 MSM_ISP_STATS_BE, 106 MSM_ISP_STATS_BHIST, 107 MSM_ISP_STATS_BF_SCALE, 108 MSM_ISP_STATS_HDR_BE, 109 MSM_ISP_STATS_HDR_BHIST, 110 MSM_ISP_STATS_AEC_BG, 111 MSM_ISP_STATS_MAX 112 }; 113 struct msm_isp_sw_framskip { 114 uint32_t stats_type_mask; 115 uint32_t stream_src_mask; 116 enum msm_vfe_frame_skip_pattern skip_mode; 117 uint32_t min_frame_id; 118 uint32_t max_frame_id; 119 }; 120 enum msm_vfe_testgen_color_pattern { 121 COLOR_BAR_8_COLOR, 122 UNICOLOR_WHITE, 123 UNICOLOR_YELLOW, 124 UNICOLOR_CYAN, 125 UNICOLOR_GREEN, 126 UNICOLOR_MAGENTA, 127 UNICOLOR_RED, 128 UNICOLOR_BLUE, 129 UNICOLOR_BLACK, 130 MAX_COLOR, 131 }; 132 enum msm_vfe_camif_input { 133 CAMIF_DISABLED, 134 CAMIF_PAD_REG_INPUT, 135 CAMIF_MIDDI_INPUT, 136 CAMIF_MIPI_INPUT, 137 }; 138 struct msm_vfe_fetch_engine_cfg { 139 uint32_t input_format; 140 uint32_t buf_width; 141 uint32_t buf_height; 142 uint32_t fetch_width; 143 uint32_t fetch_height; 144 uint32_t x_offset; 145 uint32_t y_offset; 146 uint32_t buf_stride; 147 }; 148 enum msm_vfe_camif_output_format { 149 CAMIF_QCOM_RAW, 150 CAMIF_MIPI_RAW, 151 CAMIF_PLAIN_8, 152 CAMIF_PLAIN_16, 153 CAMIF_MAX_FORMAT, 154 }; 155 struct msm_vfe_camif_subsample_cfg { 156 uint32_t irq_subsample_period; 157 uint32_t irq_subsample_pattern; 158 uint32_t sof_counter_step; 159 uint32_t pixel_skip; 160 uint32_t line_skip; 161 uint32_t first_line; 162 uint32_t last_line; 163 uint32_t first_pixel; 164 uint32_t last_pixel; 165 enum msm_vfe_camif_output_format output_format; 166 }; 167 struct msm_vfe_camif_cfg { 168 uint32_t lines_per_frame; 169 uint32_t pixels_per_line; 170 uint32_t first_pixel; 171 uint32_t last_pixel; 172 uint32_t first_line; 173 uint32_t last_line; 174 uint32_t epoch_line0; 175 uint32_t epoch_line1; 176 uint32_t is_split; 177 enum msm_vfe_camif_input camif_input; 178 struct msm_vfe_camif_subsample_cfg subsample_cfg; 179 }; 180 struct msm_vfe_testgen_cfg { 181 uint32_t lines_per_frame; 182 uint32_t pixels_per_line; 183 uint32_t v_blank; 184 uint32_t h_blank; 185 enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; 186 uint32_t rotate_period; 187 enum msm_vfe_testgen_color_pattern color_bar_pattern; 188 uint32_t burst_num_frame; 189 }; 190 enum msm_vfe_inputmux { 191 CAMIF, 192 TESTGEN, 193 EXTERNAL_READ, 194 }; 195 enum msm_vfe_stats_composite_group { 196 STATS_COMPOSITE_GRP_NONE, 197 STATS_COMPOSITE_GRP_1, 198 STATS_COMPOSITE_GRP_2, 199 STATS_COMPOSITE_GRP_MAX, 200 }; 201 enum msm_vfe_hvx_streaming_cmd { 202 HVX_DISABLE, 203 HVX_ONE_WAY, 204 HVX_ROUND_TRIP 205 }; 206 struct msm_vfe_pix_cfg { 207 struct msm_vfe_camif_cfg camif_cfg; 208 struct msm_vfe_testgen_cfg testgen_cfg; 209 struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; 210 enum msm_vfe_inputmux input_mux; 211 enum ISP_START_PIXEL_PATTERN pixel_pattern; 212 uint32_t input_format; 213 enum msm_vfe_hvx_streaming_cmd hvx_cmd; 214 uint32_t is_split; 215 }; 216 struct msm_vfe_rdi_cfg { 217 uint8_t cid; 218 uint8_t frame_based; 219 }; 220 struct msm_vfe_input_cfg { 221 union { 222 struct msm_vfe_pix_cfg pix_cfg; 223 struct msm_vfe_rdi_cfg rdi_cfg; 224 } d; 225 enum msm_vfe_input_src input_src; 226 uint32_t input_pix_clk; 227 }; 228 struct msm_vfe_fetch_eng_start { 229 uint32_t session_id; 230 uint32_t stream_id; 231 uint32_t buf_idx; 232 uint8_t offline_mode; 233 uint32_t fd; 234 uint32_t buf_addr; 235 uint32_t frame_id; 236 }; 237 enum msm_vfe_fetch_eng_pass { 238 OFFLINE_FIRST_PASS, 239 OFFLINE_SECOND_PASS, 240 OFFLINE_MAX_PASS, 241 }; 242 struct msm_vfe_fetch_eng_multi_pass_start { 243 uint32_t session_id; 244 uint32_t stream_id; 245 uint32_t buf_idx; 246 uint8_t offline_mode; 247 uint32_t fd; 248 uint32_t buf_addr; 249 uint32_t frame_id; 250 uint32_t output_buf_idx; 251 uint32_t input_buf_offset; 252 enum msm_vfe_fetch_eng_pass offline_pass; 253 uint32_t output_stream_id; 254 }; 255 struct msm_vfe_axi_plane_cfg { 256 uint32_t output_width; 257 uint32_t output_height; 258 uint32_t output_stride; 259 uint32_t output_scan_lines; 260 uint32_t output_plane_format; 261 uint32_t plane_addr_offset; 262 uint8_t csid_src; 263 uint8_t rdi_cid; 264 }; 265 enum msm_stream_rdi_input_type { 266 MSM_CAMERA_RDI_MIN, 267 MSM_CAMERA_RDI_PDAF, 268 MSM_CAMERA_RDI_MAX, 269 }; 270 struct msm_vfe_axi_stream_request_cmd { 271 uint32_t session_id; 272 uint32_t stream_id; 273 uint32_t vt_enable; 274 uint32_t output_format; 275 enum msm_vfe_axi_stream_src stream_src; 276 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 277 uint32_t burst_count; 278 uint32_t hfr_mode; 279 uint8_t frame_base; 280 uint32_t init_frame_drop; 281 enum msm_vfe_frame_skip_pattern frame_skip_pattern; 282 uint8_t buf_divert; 283 uint32_t axi_stream_handle; 284 uint32_t controllable_output; 285 uint32_t burst_len; 286 enum msm_stream_rdi_input_type rdi_input_type; 287 }; 288 struct msm_vfe_axi_stream_release_cmd { 289 uint32_t stream_handle; 290 }; 291 enum msm_vfe_axi_stream_cmd { 292 STOP_STREAM, 293 START_STREAM, 294 STOP_IMMEDIATELY, 295 }; 296 struct msm_vfe_axi_stream_cfg_cmd { 297 uint8_t num_streams; 298 uint32_t stream_handle[VFE_AXI_SRC_MAX]; 299 enum msm_vfe_axi_stream_cmd cmd; 300 uint8_t sync_frame_id_src; 301 }; 302 enum msm_vfe_axi_stream_update_type { 303 ENABLE_STREAM_BUF_DIVERT, 304 DISABLE_STREAM_BUF_DIVERT, 305 UPDATE_STREAM_FRAMEDROP_PATTERN, 306 UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, 307 UPDATE_STREAM_AXI_CONFIG, 308 UPDATE_STREAM_REQUEST_FRAMES, 309 UPDATE_STREAM_ADD_BUFQ, 310 UPDATE_STREAM_REMOVE_BUFQ, 311 UPDATE_STREAM_SW_FRAME_DROP, 312 UPDATE_STREAM_REQUEST_FRAMES_VER2, 313 UPDATE_STREAM_OFFLINE_AXI_CONFIG, 314 }; 315 #define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2 316 enum msm_vfe_iommu_type { 317 IOMMU_ATTACH, 318 IOMMU_DETACH, 319 }; 320 enum msm_vfe_buff_queue_id { 321 VFE_BUF_QUEUE_DEFAULT, 322 VFE_BUF_QUEUE_SHARED, 323 VFE_BUF_QUEUE_MAX, 324 }; 325 struct msm_vfe_axi_stream_cfg_update_info { 326 uint32_t stream_handle; 327 uint32_t output_format; 328 uint32_t user_stream_id; 329 uint32_t frame_id; 330 enum msm_vfe_frame_skip_pattern skip_pattern; 331 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 332 struct msm_isp_sw_framskip sw_skip_info; 333 }; 334 struct msm_vfe_axi_stream_cfg_update_info_req_frm { 335 uint32_t stream_handle; 336 uint32_t user_stream_id; 337 uint32_t frame_id; 338 uint32_t buf_index; 339 }; 340 struct msm_vfe_axi_halt_cmd { 341 uint32_t stop_camif; 342 uint32_t overflow_detected; 343 uint32_t blocking_halt; 344 }; 345 struct msm_vfe_axi_reset_cmd { 346 uint32_t blocking; 347 uint32_t frame_id; 348 }; 349 struct msm_vfe_axi_restart_cmd { 350 uint32_t enable_camif; 351 }; 352 struct msm_vfe_axi_stream_update_cmd { 353 uint32_t num_streams; 354 enum msm_vfe_axi_stream_update_type update_type; 355 union { 356 struct msm_vfe_axi_stream_cfg_update_info update_info[MSM_ISP_STATS_MAX]; 357 struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2; 358 }; 359 }; 360 struct msm_vfe_smmu_attach_cmd { 361 uint32_t security_mode; 362 uint32_t iommu_attach_mode; 363 }; 364 struct msm_vfe_stats_stream_request_cmd { 365 uint32_t session_id; 366 uint32_t stream_id; 367 enum msm_isp_stats_type stats_type; 368 uint32_t composite_flag; 369 uint32_t framedrop_pattern; 370 uint32_t init_frame_drop; 371 uint32_t irq_subsample_pattern; 372 uint32_t buffer_offset; 373 uint32_t stream_handle; 374 }; 375 struct msm_vfe_stats_stream_release_cmd { 376 uint32_t stream_handle; 377 }; 378 struct msm_vfe_stats_stream_cfg_cmd { 379 uint8_t num_streams; 380 uint32_t stream_handle[MSM_ISP_STATS_MAX]; 381 uint8_t enable; 382 uint32_t stats_burst_len; 383 }; 384 enum msm_vfe_reg_cfg_type { 385 VFE_WRITE, 386 VFE_WRITE_MB, 387 VFE_READ, 388 VFE_CFG_MASK, 389 VFE_WRITE_DMI_16BIT, 390 VFE_WRITE_DMI_32BIT, 391 VFE_WRITE_DMI_64BIT, 392 VFE_READ_DMI_16BIT, 393 VFE_READ_DMI_32BIT, 394 VFE_READ_DMI_64BIT, 395 GET_MAX_CLK_RATE, 396 GET_CLK_RATES, 397 GET_ISP_ID, 398 VFE_HW_UPDATE_LOCK, 399 VFE_HW_UPDATE_UNLOCK, 400 SET_WM_UB_SIZE, 401 SET_UB_POLICY, 402 GET_VFE_HW_LIMIT, 403 }; 404 struct msm_vfe_cfg_cmd2 { 405 uint16_t num_cfg; 406 uint16_t cmd_len; 407 void * cfg_data; 408 void * cfg_cmd; 409 }; 410 struct msm_vfe_cfg_cmd_list { 411 struct msm_vfe_cfg_cmd2 cfg_cmd; 412 struct msm_vfe_cfg_cmd_list * next; 413 uint32_t next_size; 414 }; 415 struct msm_vfe_reg_rw_info { 416 uint32_t reg_offset; 417 uint32_t cmd_data_offset; 418 uint32_t len; 419 }; 420 struct msm_vfe_reg_mask_info { 421 uint32_t reg_offset; 422 uint32_t mask; 423 uint32_t val; 424 }; 425 struct msm_vfe_reg_dmi_info { 426 uint32_t hi_tbl_offset; 427 uint32_t lo_tbl_offset; 428 uint32_t len; 429 }; 430 struct msm_vfe_reg_cfg_cmd { 431 union { 432 struct msm_vfe_reg_rw_info rw_info; 433 struct msm_vfe_reg_mask_info mask_info; 434 struct msm_vfe_reg_dmi_info dmi_info; 435 } u; 436 enum msm_vfe_reg_cfg_type cmd_type; 437 }; 438 enum vfe_sd_type { 439 VFE_SD_0 = 0, 440 VFE_SD_1, 441 VFE_SD_COMMON, 442 VFE_SD_MAX, 443 }; 444 #define MS_NUM_SLAVE_MAX 1 445 enum msm_vfe_dual_hw_type { 446 DUAL_NONE = 0, 447 DUAL_HW_VFE_SPLIT = 1, 448 DUAL_HW_MASTER_SLAVE = 2, 449 }; 450 enum msm_vfe_dual_hw_ms_type { 451 MS_TYPE_NONE, 452 MS_TYPE_MASTER, 453 MS_TYPE_SLAVE, 454 }; 455 struct msm_isp_set_dual_hw_ms_cmd { 456 uint8_t num_src; 457 enum msm_vfe_dual_hw_ms_type dual_hw_ms_type; 458 enum msm_vfe_input_src primary_intf; 459 enum msm_vfe_input_src input_src[VFE_SRC_MAX]; 460 uint32_t sof_delta_threshold; 461 }; 462 enum msm_isp_buf_type { 463 ISP_PRIVATE_BUF, 464 ISP_SHARE_BUF, 465 MAX_ISP_BUF_TYPE, 466 }; 467 struct msm_isp_unmap_buf_req { 468 uint32_t fd; 469 }; 470 struct msm_isp_buf_request { 471 uint32_t session_id; 472 uint32_t stream_id; 473 uint8_t num_buf; 474 uint32_t handle; 475 enum msm_isp_buf_type buf_type; 476 }; 477 struct msm_isp_buf_request_ver2 { 478 uint32_t session_id; 479 uint32_t stream_id; 480 uint8_t num_buf; 481 uint32_t handle; 482 enum msm_isp_buf_type buf_type; 483 enum smmu_attach_mode security_mode; 484 uint32_t reserved[4]; 485 }; 486 struct msm_isp_qbuf_plane { 487 uint32_t addr; 488 uint32_t offset; 489 uint32_t length; 490 }; 491 struct msm_isp_qbuf_buffer { 492 struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; 493 uint32_t num_planes; 494 }; 495 struct msm_isp_qbuf_info { 496 uint32_t handle; 497 int32_t buf_idx; 498 struct msm_isp_qbuf_buffer buffer; 499 uint32_t dirty_buf; 500 }; 501 struct msm_isp_clk_rates { 502 uint32_t svs_rate; 503 uint32_t nominal_rate; 504 uint32_t high_rate; 505 }; 506 struct msm_vfe_axi_src_state { 507 enum msm_vfe_input_src input_src; 508 uint32_t src_active; 509 uint32_t src_frame_id; 510 }; 511 enum msm_isp_event_mask_index { 512 ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0, 513 ISP_EVENT_MASK_INDEX_ERROR = 1, 514 ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2, 515 ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3, 516 ISP_EVENT_MASK_INDEX_REG_UPDATE = 4, 517 ISP_EVENT_MASK_INDEX_SOF = 5, 518 ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, 519 ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, 520 ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8, 521 ISP_EVENT_MASK_INDEX_BUF_DONE = 9, 522 ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10, 523 ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11, 524 ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12, 525 }; 526 #define ISP_EVENT_SUBS_MASK_NONE 0 527 #define ISP_EVENT_SUBS_MASK_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY) 528 #define ISP_EVENT_SUBS_MASK_ERROR (1 << ISP_EVENT_MASK_INDEX_ERROR) 529 #define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT) 530 #define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE) 531 #define ISP_EVENT_SUBS_MASK_REG_UPDATE (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE) 532 #define ISP_EVENT_SUBS_MASK_SOF (1 << ISP_EVENT_MASK_INDEX_SOF) 533 #define ISP_EVENT_SUBS_MASK_BUF_DIVERT (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT) 534 #define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY) 535 #define ISP_EVENT_SUBS_MASK_FE_READ_DONE (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) 536 #define ISP_EVENT_SUBS_MASK_BUF_DONE (1 << ISP_EVENT_MASK_INDEX_BUF_DONE) 537 #define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING) 538 #define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH) 539 #define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR) 540 enum msm_isp_event_idx { 541 ISP_REG_UPDATE = 0, 542 ISP_EPOCH_0 = 1, 543 ISP_EPOCH_1 = 2, 544 ISP_START_ACK = 3, 545 ISP_STOP_ACK = 4, 546 ISP_IRQ_VIOLATION = 5, 547 ISP_STATS_OVERFLOW = 6, 548 ISP_BUF_DONE = 7, 549 ISP_FE_RD_DONE = 8, 550 ISP_IOMMU_P_FAULT = 9, 551 ISP_ERROR = 10, 552 ISP_HW_FATAL_ERROR = 11, 553 ISP_PING_PONG_MISMATCH = 12, 554 ISP_REG_UPDATE_MISSING = 13, 555 ISP_BUF_FATAL_ERROR = 14, 556 ISP_EVENT_MAX = 15 557 }; 558 #define ISP_EVENT_OFFSET 8 559 #define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) 560 #define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) 561 #define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) 562 #define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) 563 #define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) 564 #define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) 565 #define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) 566 #define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) 567 #define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) 568 #define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) 569 #define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) 570 #define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) 571 #define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR) 572 #define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) 573 #define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) 574 #define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) 575 #define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) 576 #define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) 577 #define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) 578 #define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) 579 #define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT) 580 #define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR) 581 #define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH) 582 #define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING) 583 #define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR) 584 #define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) 585 struct msm_isp_buf_event { 586 uint32_t session_id; 587 uint32_t stream_id; 588 uint32_t handle; 589 uint32_t output_format; 590 int8_t buf_idx; 591 }; 592 struct msm_isp_fetch_eng_event { 593 uint32_t session_id; 594 uint32_t stream_id; 595 uint32_t handle; 596 uint32_t fd; 597 int8_t buf_idx; 598 int8_t offline_mode; 599 }; 600 struct msm_isp_stats_event { 601 uint32_t stats_mask; 602 uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; 603 uint8_t pd_stats_idx; 604 }; 605 struct msm_isp_stream_ack { 606 uint32_t session_id; 607 uint32_t stream_id; 608 uint32_t handle; 609 }; 610 enum msm_vfe_error_type { 611 ISP_ERROR_NONE, 612 ISP_ERROR_CAMIF, 613 ISP_ERROR_BUS_OVERFLOW, 614 ISP_ERROR_RETURN_EMPTY_BUFFER, 615 ISP_ERROR_FRAME_ID_MISMATCH, 616 ISP_ERROR_MAX, 617 }; 618 struct msm_isp_error_info { 619 enum msm_vfe_error_type err_type; 620 uint32_t session_id; 621 uint32_t stream_id; 622 uint32_t stream_id_mask; 623 }; 624 struct msm_isp_ms_delta_info { 625 uint8_t num_delta_info; 626 uint32_t delta[MS_NUM_SLAVE_MAX]; 627 }; 628 struct msm_isp_output_info { 629 uint8_t regs_not_updated; 630 uint16_t output_err_mask; 631 uint8_t stream_framedrop_mask; 632 uint16_t stats_framedrop_mask; 633 }; 634 struct msm_isp_sof_info { 635 uint8_t regs_not_updated; 636 uint16_t reg_update_fail_mask; 637 uint32_t stream_get_buf_fail_mask; 638 uint16_t stats_get_buf_fail_mask; 639 struct msm_isp_ms_delta_info ms_delta_info; 640 uint16_t axi_updating_mask; 641 uint32_t reg_update_fail_mask_ext; 642 }; 643 #define AXI_UPDATING_MASK 1 644 #define REG_UPDATE_FAIL_MASK_EXT 1 645 struct msm_isp_event_data { 646 struct timeval timestamp; 647 struct timeval mono_timestamp; 648 uint32_t frame_id; 649 union { 650 struct msm_isp_stats_event stats; 651 struct msm_isp_buf_event buf_done; 652 struct msm_isp_fetch_eng_event fetch_done; 653 struct msm_isp_error_info error_info; 654 struct msm_isp_output_info output_info; 655 struct msm_isp_sof_info sof_info; 656 } u; 657 }; 658 enum msm_vfe_ahb_clk_vote { 659 MSM_ISP_CAMERA_AHB_SVS_VOTE = 1, 660 MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2, 661 MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3, 662 MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4, 663 }; 664 struct msm_isp_ahb_clk_cfg { 665 uint32_t vote; 666 uint32_t reserved[2]; 667 }; 668 enum msm_vfe_dual_cam_sync_mode { 669 MSM_ISP_DUAL_CAM_ASYNC, 670 MSM_ISP_DUAL_CAM_SYNC, 671 }; 672 struct msm_isp_dual_hw_master_slave_sync { 673 uint32_t sync_mode; 674 uint32_t reserved[2]; 675 }; 676 struct msm_vfe_dual_lpm_mode { 677 enum msm_vfe_axi_stream_src stream_src[VFE_AXI_SRC_MAX]; 678 uint32_t num_src; 679 uint32_t lpm_mode; 680 }; 681 #define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') 682 #define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') 683 #define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') 684 #define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') 685 #define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') 686 #define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') 687 #define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') 688 #define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') 689 #define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') 690 #define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') 691 #define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') 692 #define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') 693 #define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') 694 #define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') 695 #define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') 696 #define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') 697 #define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') 698 #define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') 699 #define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') 700 #define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') 701 #define V4L2_PIX_FMT_P16BGGR12 v4l2_fourcc('P', 'B', 'G', '2') 702 #define V4L2_PIX_FMT_P16GBRG12 v4l2_fourcc('P', 'G', 'B', '2') 703 #define V4L2_PIX_FMT_P16GRBG12 v4l2_fourcc('P', 'G', 'R', '2') 704 #define V4L2_PIX_FMT_P16RGGB12 v4l2_fourcc('P', 'R', 'G', '2') 705 #define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') 706 #define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') 707 #define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') 708 #define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0') 709 #define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') 710 #define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') 711 #define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') 712 #define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') 713 enum msm_isp_ioctl_cmd_code { 714 MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE, 715 MSM_ISP_REQUEST_BUF, 716 MSM_ISP_ENQUEUE_BUF, 717 MSM_ISP_RELEASE_BUF, 718 MSM_ISP_REQUEST_STREAM, 719 MSM_ISP_CFG_STREAM, 720 MSM_ISP_RELEASE_STREAM, 721 MSM_ISP_INPUT_CFG, 722 MSM_ISP_SET_SRC_STATE, 723 MSM_ISP_REQUEST_STATS_STREAM, 724 MSM_ISP_CFG_STATS_STREAM, 725 MSM_ISP_RELEASE_STATS_STREAM, 726 MSM_ISP_REG_UPDATE_CMD, 727 MSM_ISP_UPDATE_STREAM, 728 MSM_VFE_REG_LIST_CFG, 729 MSM_ISP_SMMU_ATTACH, 730 MSM_ISP_UPDATE_STATS_STREAM, 731 MSM_ISP_AXI_HALT, 732 MSM_ISP_AXI_RESET, 733 MSM_ISP_AXI_RESTART, 734 MSM_ISP_FETCH_ENG_START, 735 MSM_ISP_DEQUEUE_BUF, 736 MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, 737 MSM_ISP_MAP_BUF_START_FE, 738 MSM_ISP_UNMAP_BUF, 739 MSM_ISP_AHB_CLK_CFG, 740 MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, 741 MSM_ISP_FETCH_ENG_MULTI_PASS_START, 742 MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, 743 MSM_ISP_REQUEST_BUF_VER2, 744 MSM_ISP_DUAL_HW_LPM_MODE, 745 }; 746 #define VIDIOC_MSM_VFE_REG_CFG _IOWR('V', MSM_VFE_REG_CFG, struct msm_vfe_cfg_cmd2) 747 #define VIDIOC_MSM_ISP_REQUEST_BUF _IOWR('V', MSM_ISP_REQUEST_BUF, struct msm_isp_buf_request) 748 #define VIDIOC_MSM_ISP_ENQUEUE_BUF _IOWR('V', MSM_ISP_ENQUEUE_BUF, struct msm_isp_qbuf_info) 749 #define VIDIOC_MSM_ISP_RELEASE_BUF _IOWR('V', MSM_ISP_RELEASE_BUF, struct msm_isp_buf_request) 750 #define VIDIOC_MSM_ISP_REQUEST_STREAM _IOWR('V', MSM_ISP_REQUEST_STREAM, struct msm_vfe_axi_stream_request_cmd) 751 #define VIDIOC_MSM_ISP_CFG_STREAM _IOWR('V', MSM_ISP_CFG_STREAM, struct msm_vfe_axi_stream_cfg_cmd) 752 #define VIDIOC_MSM_ISP_RELEASE_STREAM _IOWR('V', MSM_ISP_RELEASE_STREAM, struct msm_vfe_axi_stream_release_cmd) 753 #define VIDIOC_MSM_ISP_INPUT_CFG _IOWR('V', MSM_ISP_INPUT_CFG, struct msm_vfe_input_cfg) 754 #define VIDIOC_MSM_ISP_SET_SRC_STATE _IOWR('V', MSM_ISP_SET_SRC_STATE, struct msm_vfe_axi_src_state) 755 #define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM _IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, struct msm_vfe_stats_stream_request_cmd) 756 #define VIDIOC_MSM_ISP_CFG_STATS_STREAM _IOWR('V', MSM_ISP_CFG_STATS_STREAM, struct msm_vfe_stats_stream_cfg_cmd) 757 #define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM _IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, struct msm_vfe_stats_stream_release_cmd) 758 #define VIDIOC_MSM_ISP_REG_UPDATE_CMD _IOWR('V', MSM_ISP_REG_UPDATE_CMD, enum msm_vfe_input_src) 759 #define VIDIOC_MSM_ISP_UPDATE_STREAM _IOWR('V', MSM_ISP_UPDATE_STREAM, struct msm_vfe_axi_stream_update_cmd) 760 #define VIDIOC_MSM_VFE_REG_LIST_CFG _IOWR('V', MSM_VFE_REG_LIST_CFG, struct msm_vfe_cfg_cmd_list) 761 #define VIDIOC_MSM_ISP_SMMU_ATTACH _IOWR('V', MSM_ISP_SMMU_ATTACH, struct msm_vfe_smmu_attach_cmd) 762 #define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM _IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, struct msm_vfe_axi_stream_update_cmd) 763 #define VIDIOC_MSM_ISP_AXI_HALT _IOWR('V', MSM_ISP_AXI_HALT, struct msm_vfe_axi_halt_cmd) 764 #define VIDIOC_MSM_ISP_AXI_RESET _IOWR('V', MSM_ISP_AXI_RESET, struct msm_vfe_axi_reset_cmd) 765 #define VIDIOC_MSM_ISP_AXI_RESTART _IOWR('V', MSM_ISP_AXI_RESTART, struct msm_vfe_axi_restart_cmd) 766 #define VIDIOC_MSM_ISP_FETCH_ENG_START _IOWR('V', MSM_ISP_FETCH_ENG_START, struct msm_vfe_fetch_eng_start) 767 #define VIDIOC_MSM_ISP_DEQUEUE_BUF _IOWR('V', MSM_ISP_DEQUEUE_BUF, struct msm_isp_qbuf_info) 768 #define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE _IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, struct msm_isp_set_dual_hw_ms_cmd) 769 #define VIDIOC_MSM_ISP_MAP_BUF_START_FE _IOWR('V', MSM_ISP_MAP_BUF_START_FE, struct msm_vfe_fetch_eng_start) 770 #define VIDIOC_MSM_ISP_UNMAP_BUF _IOWR('V', MSM_ISP_UNMAP_BUF, struct msm_isp_unmap_buf_req) 771 #define VIDIOC_MSM_ISP_AHB_CLK_CFG _IOWR('V', MSM_ISP_AHB_CLK_CFG, struct msm_isp_ahb_clk_cfg) 772 #define VIDIOC_MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC _IOWR('V', MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, struct msm_isp_dual_hw_master_slave_sync) 773 #define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, struct msm_vfe_fetch_eng_multi_pass_start) 774 #define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, struct msm_vfe_fetch_eng_multi_pass_start) 775 #define VIDIOC_MSM_ISP_REQUEST_BUF_VER2 _IOWR('V', MSM_ISP_REQUEST_BUF_VER2, struct msm_isp_buf_request_ver2) 776 #define VIDIOC_MSM_ISP_DUAL_HW_LPM_MODE _IOWR('V', MSM_ISP_DUAL_HW_LPM_MODE, struct msm_vfe_dual_lpm_mode) 777 #endif 778 779