1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef IPA_QMI_SERVICE_V01_H 20 #define IPA_QMI_SERVICE_V01_H 21 #define QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01 2 22 #define QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01 2 23 #define QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01 2 24 #define QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01 2 25 #define QMI_IPA_MAX_FILTERS_V01 64 26 #define QMI_IPA_MAX_FILTERS_EX_V01 128 27 #define QMI_IPA_MAX_PIPES_V01 20 28 #define QMI_IPA_MAX_APN_V01 8 29 #define QMI_IPA_MAX_PER_CLIENTS_V01 64 30 #define QMI_IPA_MAX_CLIENT_DST_PIPES_V01 8 31 #define QMI_IPA_MAX_UL_FIREWALL_RULES_V01 64 32 #define IPA_QMI_SUPPORTS_STATS 33 #define IPA_INT_MAX ((int) (~0U >> 1)) 34 #define IPA_INT_MIN (- IPA_INT_MAX - 1) 35 enum ipa_qmi_result_type_v01 { 36 IPA_QMI_RESULT_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, 37 IPA_QMI_RESULT_SUCCESS_V01 = 0, 38 IPA_QMI_RESULT_FAILURE_V01 = 1, 39 IPA_QMI_RESULT_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, 40 }; 41 enum ipa_qmi_error_type_v01 { 42 IPA_QMI_ERROR_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, 43 IPA_QMI_ERR_NONE_V01 = 0x0000, 44 IPA_QMI_ERR_MALFORMED_MSG_V01 = 0x0001, 45 IPA_QMI_ERR_NO_MEMORY_V01 = 0x0002, 46 IPA_QMI_ERR_INTERNAL_V01 = 0x0003, 47 IPA_QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 = 0x0005, 48 IPA_QMI_ERR_INVALID_ID_V01 = 0x0029, 49 IPA_QMI_ERR_ENCODING_V01 = 0x003A, 50 IPA_QMI_ERR_INCOMPATIBLE_STATE_V01 = 0x005A, 51 IPA_QMI_ERR_NOT_SUPPORTED_V01 = 0x005E, 52 IPA_QMI_ERROR_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, 53 }; 54 struct ipa_qmi_response_type_v01 { 55 enum ipa_qmi_result_type_v01 result; 56 enum ipa_qmi_error_type_v01 error; 57 }; 58 enum ipa_platform_type_enum_v01 { 59 IPA_PLATFORM_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 60 QMI_IPA_PLATFORM_TYPE_INVALID_V01 = 0, 61 QMI_IPA_PLATFORM_TYPE_TN_V01 = 1, 62 QMI_IPA_PLATFORM_TYPE_LE_V01 = 2, 63 QMI_IPA_PLATFORM_TYPE_MSM_ANDROID_V01 = 3, 64 QMI_IPA_PLATFORM_TYPE_MSM_WINDOWS_V01 = 4, 65 QMI_IPA_PLATFORM_TYPE_MSM_QNX_V01 = 5, 66 IPA_PLATFORM_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 67 }; 68 struct ipa_hdr_tbl_info_type_v01 { 69 uint32_t modem_offset_start; 70 uint32_t modem_offset_end; 71 }; 72 struct ipa_route_tbl_info_type_v01 { 73 uint32_t route_tbl_start_addr; 74 uint32_t num_indices; 75 }; 76 struct ipa_modem_mem_info_type_v01 { 77 uint32_t block_start_addr; 78 uint32_t size; 79 }; 80 struct ipa_hdr_proc_ctx_tbl_info_type_v01 { 81 uint32_t modem_offset_start; 82 uint32_t modem_offset_end; 83 }; 84 struct ipa_zip_tbl_info_type_v01 { 85 uint32_t modem_offset_start; 86 uint32_t modem_offset_end; 87 }; 88 struct ipa_init_modem_driver_req_msg_v01 { 89 uint8_t platform_type_valid; 90 enum ipa_platform_type_enum_v01 platform_type; 91 uint8_t hdr_tbl_info_valid; 92 struct ipa_hdr_tbl_info_type_v01 hdr_tbl_info; 93 uint8_t v4_route_tbl_info_valid; 94 struct ipa_route_tbl_info_type_v01 v4_route_tbl_info; 95 uint8_t v6_route_tbl_info_valid; 96 struct ipa_route_tbl_info_type_v01 v6_route_tbl_info; 97 uint8_t v4_filter_tbl_start_addr_valid; 98 uint32_t v4_filter_tbl_start_addr; 99 uint8_t v6_filter_tbl_start_addr_valid; 100 uint32_t v6_filter_tbl_start_addr; 101 uint8_t modem_mem_info_valid; 102 struct ipa_modem_mem_info_type_v01 modem_mem_info; 103 uint8_t ctrl_comm_dest_end_pt_valid; 104 uint32_t ctrl_comm_dest_end_pt; 105 uint8_t is_ssr_bootup_valid; 106 uint8_t is_ssr_bootup; 107 uint8_t hdr_proc_ctx_tbl_info_valid; 108 struct ipa_hdr_proc_ctx_tbl_info_type_v01 hdr_proc_ctx_tbl_info; 109 uint8_t zip_tbl_info_valid; 110 struct ipa_zip_tbl_info_type_v01 zip_tbl_info; 111 uint8_t v4_hash_route_tbl_info_valid; 112 struct ipa_route_tbl_info_type_v01 v4_hash_route_tbl_info; 113 uint8_t v6_hash_route_tbl_info_valid; 114 struct ipa_route_tbl_info_type_v01 v6_hash_route_tbl_info; 115 uint8_t v4_hash_filter_tbl_start_addr_valid; 116 uint32_t v4_hash_filter_tbl_start_addr; 117 uint8_t v6_hash_filter_tbl_start_addr_valid; 118 uint32_t v6_hash_filter_tbl_start_addr; 119 uint8_t hw_stats_quota_base_addr_valid; 120 uint32_t hw_stats_quota_base_addr; 121 uint8_t hw_stats_quota_size_valid; 122 uint32_t hw_stats_quota_size; 123 uint8_t hw_drop_stats_base_addr_valid; 124 uint32_t hw_drop_stats_base_addr; 125 uint8_t hw_drop_stats_table_size_valid; 126 uint32_t hw_drop_stats_table_size; 127 }; 128 struct ipa_init_modem_driver_resp_msg_v01 { 129 struct ipa_qmi_response_type_v01 resp; 130 uint8_t ctrl_comm_dest_end_pt_valid; 131 uint32_t ctrl_comm_dest_end_pt; 132 uint8_t default_end_pt_valid; 133 uint32_t default_end_pt; 134 uint8_t modem_driver_init_pending_valid; 135 uint8_t modem_driver_init_pending; 136 }; 137 struct ipa_init_modem_driver_cmplt_req_msg_v01 { 138 uint8_t status; 139 }; 140 struct ipa_init_modem_driver_cmplt_resp_msg_v01 { 141 struct ipa_qmi_response_type_v01 resp; 142 }; 143 struct ipa_indication_reg_req_msg_v01 { 144 uint8_t master_driver_init_complete_valid; 145 uint8_t master_driver_init_complete; 146 uint8_t data_usage_quota_reached_valid; 147 uint8_t data_usage_quota_reached; 148 }; 149 struct ipa_indication_reg_resp_msg_v01 { 150 struct ipa_qmi_response_type_v01 resp; 151 }; 152 struct ipa_master_driver_init_complt_ind_msg_v01 { 153 struct ipa_qmi_response_type_v01 master_driver_init_status; 154 }; 155 struct ipa_ipfltr_range_eq_16_type_v01 { 156 uint8_t offset; 157 uint16_t range_low; 158 uint16_t range_high; 159 }; 160 struct ipa_ipfltr_mask_eq_32_type_v01 { 161 uint8_t offset; 162 uint32_t mask; 163 uint32_t value; 164 }; 165 struct ipa_ipfltr_eq_16_type_v01 { 166 uint8_t offset; 167 uint16_t value; 168 }; 169 struct ipa_ipfltr_eq_32_type_v01 { 170 uint8_t offset; 171 uint32_t value; 172 }; 173 struct ipa_ipfltr_mask_eq_128_type_v01 { 174 uint8_t offset; 175 uint8_t mask[16]; 176 uint8_t value[16]; 177 }; 178 struct ipa_filter_rule_type_v01 { 179 uint16_t rule_eq_bitmap; 180 uint8_t tos_eq_present; 181 uint8_t tos_eq; 182 uint8_t protocol_eq_present; 183 uint8_t protocol_eq; 184 uint8_t num_ihl_offset_range_16; 185 struct ipa_ipfltr_range_eq_16_type_v01 ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01]; 186 uint8_t num_offset_meq_32; 187 struct ipa_ipfltr_mask_eq_32_type_v01 offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01]; 188 uint8_t tc_eq_present; 189 uint8_t tc_eq; 190 uint8_t flow_eq_present; 191 uint32_t flow_eq; 192 uint8_t ihl_offset_eq_16_present; 193 struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16; 194 uint8_t ihl_offset_eq_32_present; 195 struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32; 196 uint8_t num_ihl_offset_meq_32; 197 struct ipa_ipfltr_mask_eq_32_type_v01 ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01]; 198 uint8_t num_offset_meq_128; 199 struct ipa_ipfltr_mask_eq_128_type_v01 offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01]; 200 uint8_t metadata_meq32_present; 201 struct ipa_ipfltr_mask_eq_32_type_v01 metadata_meq32; 202 uint8_t ipv4_frag_eq_present; 203 }; 204 enum ipa_ip_type_enum_v01 { 205 IPA_IP_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 206 QMI_IPA_IP_TYPE_INVALID_V01 = 0, 207 QMI_IPA_IP_TYPE_V4_V01 = 1, 208 QMI_IPA_IP_TYPE_V6_V01 = 2, 209 QMI_IPA_IP_TYPE_V4V6_V01 = 3, 210 IPA_IP_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 211 }; 212 enum ipa_filter_action_enum_v01 { 213 IPA_FILTER_ACTION_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 214 QMI_IPA_FILTER_ACTION_INVALID_V01 = 0, 215 QMI_IPA_FILTER_ACTION_SRC_NAT_V01 = 1, 216 QMI_IPA_FILTER_ACTION_DST_NAT_V01 = 2, 217 QMI_IPA_FILTER_ACTION_ROUTING_V01 = 3, 218 QMI_IPA_FILTER_ACTION_EXCEPTION_V01 = 4, 219 IPA_FILTER_ACTION_ENUM_MAX_ENUM_VAL_V01 = 2147483647 220 }; 221 struct ipa_filter_spec_type_v01 { 222 uint32_t filter_spec_identifier; 223 enum ipa_ip_type_enum_v01 ip_type; 224 struct ipa_filter_rule_type_v01 filter_rule; 225 enum ipa_filter_action_enum_v01 filter_action; 226 uint8_t is_routing_table_index_valid; 227 uint32_t route_table_index; 228 uint8_t is_mux_id_valid; 229 uint32_t mux_id; 230 }; 231 struct ipa_filter_spec_ex_type_v01 { 232 enum ipa_ip_type_enum_v01 ip_type; 233 struct ipa_filter_rule_type_v01 filter_rule; 234 enum ipa_filter_action_enum_v01 filter_action; 235 uint8_t is_routing_table_index_valid; 236 uint32_t route_table_index; 237 uint8_t is_mux_id_valid; 238 uint32_t mux_id; 239 uint32_t rule_id; 240 uint8_t is_rule_hashable; 241 }; 242 struct ipa_install_fltr_rule_req_msg_v01 { 243 uint8_t filter_spec_list_valid; 244 uint32_t filter_spec_list_len; 245 struct ipa_filter_spec_type_v01 filter_spec_list[QMI_IPA_MAX_FILTERS_V01]; 246 uint8_t source_pipe_index_valid; 247 uint32_t source_pipe_index; 248 uint8_t num_ipv4_filters_valid; 249 uint32_t num_ipv4_filters; 250 uint8_t num_ipv6_filters_valid; 251 uint32_t num_ipv6_filters; 252 uint8_t xlat_filter_indices_list_valid; 253 uint32_t xlat_filter_indices_list_len; 254 uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01]; 255 uint8_t filter_spec_ex_list_valid; 256 uint32_t filter_spec_ex_list_len; 257 struct ipa_filter_spec_ex_type_v01 filter_spec_ex_list[QMI_IPA_MAX_FILTERS_V01]; 258 }; 259 struct ipa_filter_rule_identifier_to_handle_map_v01 { 260 uint32_t filter_spec_identifier; 261 uint32_t filter_handle; 262 }; 263 struct ipa_install_fltr_rule_resp_msg_v01 { 264 struct ipa_qmi_response_type_v01 resp; 265 uint8_t filter_handle_list_valid; 266 uint32_t filter_handle_list_len; 267 struct ipa_filter_rule_identifier_to_handle_map_v01 filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; 268 uint8_t rule_id_valid; 269 uint32_t rule_id_len; 270 uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01]; 271 }; 272 struct ipa_filter_handle_to_index_map_v01 { 273 uint32_t filter_handle; 274 uint32_t filter_index; 275 }; 276 struct ipa_fltr_installed_notif_req_msg_v01 { 277 uint32_t source_pipe_index; 278 enum ipa_qmi_result_type_v01 install_status; 279 uint32_t filter_index_list_len; 280 struct ipa_filter_handle_to_index_map_v01 filter_index_list[QMI_IPA_MAX_FILTERS_V01]; 281 uint8_t embedded_pipe_index_valid; 282 uint32_t embedded_pipe_index; 283 uint8_t retain_header_valid; 284 uint8_t retain_header; 285 uint8_t embedded_call_mux_id_valid; 286 uint32_t embedded_call_mux_id; 287 uint8_t num_ipv4_filters_valid; 288 uint32_t num_ipv4_filters; 289 uint8_t num_ipv6_filters_valid; 290 uint32_t num_ipv6_filters; 291 uint8_t start_ipv4_filter_idx_valid; 292 uint32_t start_ipv4_filter_idx; 293 uint8_t start_ipv6_filter_idx_valid; 294 uint32_t start_ipv6_filter_idx; 295 uint8_t rule_id_valid; 296 uint32_t rule_id_len; 297 uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01]; 298 uint8_t dst_pipe_id_valid; 299 uint32_t dst_pipe_id_len; 300 uint32_t dst_pipe_id[QMI_IPA_MAX_CLIENT_DST_PIPES_V01]; 301 }; 302 struct ipa_fltr_installed_notif_resp_msg_v01 { 303 struct ipa_qmi_response_type_v01 resp; 304 }; 305 struct ipa_enable_force_clear_datapath_req_msg_v01 { 306 uint32_t source_pipe_bitmask; 307 uint32_t request_id; 308 uint8_t throttle_source_valid; 309 uint8_t throttle_source; 310 }; 311 struct ipa_enable_force_clear_datapath_resp_msg_v01 { 312 struct ipa_qmi_response_type_v01 resp; 313 }; 314 struct ipa_disable_force_clear_datapath_req_msg_v01 { 315 uint32_t request_id; 316 }; 317 struct ipa_disable_force_clear_datapath_resp_msg_v01 { 318 struct ipa_qmi_response_type_v01 resp; 319 }; 320 enum ipa_peripheral_speed_enum_v01 { 321 IPA_PERIPHERAL_SPEED_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 322 QMI_IPA_PER_USB_FS_V01 = 1, 323 QMI_IPA_PER_USB_HS_V01 = 2, 324 QMI_IPA_PER_USB_SS_V01 = 3, 325 QMI_IPA_PER_WLAN_V01 = 4, 326 IPA_PERIPHERAL_SPEED_ENUM_MAX_ENUM_VAL_V01 = 2147483647 327 }; 328 enum ipa_pipe_mode_enum_v01 { 329 IPA_PIPE_MODE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 330 QMI_IPA_PIPE_MODE_HW_V01 = 1, 331 QMI_IPA_PIPE_MODE_SW_V01 = 2, 332 IPA_PIPE_MODE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 333 }; 334 enum ipa_peripheral_type_enum_v01 { 335 IPA_PERIPHERAL_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 336 QMI_IPA_PERIPHERAL_USB_V01 = 1, 337 QMI_IPA_PERIPHERAL_HSIC_V01 = 2, 338 QMI_IPA_PERIPHERAL_PCIE_V01 = 3, 339 IPA_PERIPHERAL_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 340 }; 341 struct ipa_config_req_msg_v01 { 342 uint8_t peripheral_type_valid; 343 enum ipa_peripheral_type_enum_v01 peripheral_type; 344 uint8_t hw_deaggr_supported_valid; 345 uint8_t hw_deaggr_supported; 346 uint8_t max_aggr_frame_size_valid; 347 uint32_t max_aggr_frame_size; 348 uint8_t ipa_ingress_pipe_mode_valid; 349 enum ipa_pipe_mode_enum_v01 ipa_ingress_pipe_mode; 350 uint8_t peripheral_speed_info_valid; 351 enum ipa_peripheral_speed_enum_v01 peripheral_speed_info; 352 uint8_t dl_accumulation_time_limit_valid; 353 uint32_t dl_accumulation_time_limit; 354 uint8_t dl_accumulation_pkt_limit_valid; 355 uint32_t dl_accumulation_pkt_limit; 356 uint8_t dl_accumulation_byte_limit_valid; 357 uint32_t dl_accumulation_byte_limit; 358 uint8_t ul_accumulation_time_limit_valid; 359 uint32_t ul_accumulation_time_limit; 360 uint8_t hw_control_flags_valid; 361 uint32_t hw_control_flags; 362 uint8_t ul_msi_event_threshold_valid; 363 uint32_t ul_msi_event_threshold; 364 uint8_t dl_msi_event_threshold_valid; 365 uint32_t dl_msi_event_threshold; 366 uint8_t ul_fifo_size_valid; 367 uint32_t ul_fifo_size; 368 uint8_t dl_fifo_size_valid; 369 uint32_t dl_fifo_size; 370 uint8_t dl_buf_size_valid; 371 uint32_t dl_buf_size; 372 }; 373 struct ipa_config_resp_msg_v01 { 374 struct ipa_qmi_response_type_v01 resp; 375 }; 376 enum ipa_stats_type_enum_v01 { 377 IPA_STATS_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 378 QMI_IPA_STATS_TYPE_INVALID_V01 = 0, 379 QMI_IPA_STATS_TYPE_PIPE_V01 = 1, 380 QMI_IPA_STATS_TYPE_FILTER_RULES_V01 = 2, 381 IPA_STATS_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 382 }; 383 struct ipa_pipe_stats_info_type_v01 { 384 uint32_t pipe_index; 385 uint64_t num_ipv4_packets; 386 uint64_t num_ipv4_bytes; 387 uint64_t num_ipv6_packets; 388 uint64_t num_ipv6_bytes; 389 }; 390 struct ipa_stats_type_filter_rule_v01 { 391 uint32_t filter_rule_index; 392 uint64_t num_packets; 393 }; 394 struct ipa_get_data_stats_req_msg_v01 { 395 enum ipa_stats_type_enum_v01 ipa_stats_type; 396 uint8_t reset_stats_valid; 397 uint8_t reset_stats; 398 }; 399 struct ipa_get_data_stats_resp_msg_v01 { 400 struct ipa_qmi_response_type_v01 resp; 401 uint8_t ipa_stats_type_valid; 402 enum ipa_stats_type_enum_v01 ipa_stats_type; 403 uint8_t ul_src_pipe_stats_list_valid; 404 uint32_t ul_src_pipe_stats_list_len; 405 struct ipa_pipe_stats_info_type_v01 ul_src_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; 406 uint8_t dl_dst_pipe_stats_list_valid; 407 uint32_t dl_dst_pipe_stats_list_len; 408 struct ipa_pipe_stats_info_type_v01 dl_dst_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; 409 uint8_t dl_filter_rule_stats_list_valid; 410 uint32_t dl_filter_rule_stats_list_len; 411 struct ipa_stats_type_filter_rule_v01 dl_filter_rule_stats_list[QMI_IPA_MAX_FILTERS_V01]; 412 }; 413 struct ipa_apn_data_stats_info_type_v01 { 414 uint32_t mux_id; 415 uint64_t num_ul_packets; 416 uint64_t num_ul_bytes; 417 uint64_t num_dl_packets; 418 uint64_t num_dl_bytes; 419 }; 420 struct ipa_get_apn_data_stats_req_msg_v01 { 421 uint8_t mux_id_list_valid; 422 uint32_t mux_id_list_len; 423 uint32_t mux_id_list[QMI_IPA_MAX_APN_V01]; 424 }; 425 struct ipa_get_apn_data_stats_resp_msg_v01 { 426 struct ipa_qmi_response_type_v01 resp; 427 uint8_t apn_data_stats_list_valid; 428 uint32_t apn_data_stats_list_len; 429 struct ipa_apn_data_stats_info_type_v01 apn_data_stats_list[QMI_IPA_MAX_APN_V01]; 430 }; 431 struct ipa_data_usage_quota_info_type_v01 { 432 uint32_t mux_id; 433 uint64_t num_Mbytes; 434 }; 435 struct ipa_set_data_usage_quota_req_msg_v01 { 436 uint8_t apn_quota_list_valid; 437 uint32_t apn_quota_list_len; 438 struct ipa_data_usage_quota_info_type_v01 apn_quota_list[QMI_IPA_MAX_APN_V01]; 439 }; 440 struct ipa_set_data_usage_quota_resp_msg_v01 { 441 struct ipa_qmi_response_type_v01 resp; 442 }; 443 struct ipa_data_usage_quota_reached_ind_msg_v01 { 444 struct ipa_data_usage_quota_info_type_v01 apn; 445 }; 446 struct ipa_stop_data_usage_quota_req_msg_v01 { 447 char __placeholder; 448 }; 449 struct ipa_stop_data_usage_quota_resp_msg_v01 { 450 struct ipa_qmi_response_type_v01 resp; 451 }; 452 struct ipa_install_fltr_rule_req_ex_msg_v01 { 453 uint8_t filter_spec_ex_list_valid; 454 uint32_t filter_spec_ex_list_len; 455 struct ipa_filter_spec_ex_type_v01 filter_spec_ex_list[QMI_IPA_MAX_FILTERS_EX_V01]; 456 uint8_t source_pipe_index_valid; 457 uint32_t source_pipe_index; 458 uint8_t num_ipv4_filters_valid; 459 uint32_t num_ipv4_filters; 460 uint8_t num_ipv6_filters_valid; 461 uint32_t num_ipv6_filters; 462 uint8_t xlat_filter_indices_list_valid; 463 uint32_t xlat_filter_indices_list_len; 464 uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_EX_V01]; 465 }; 466 struct ipa_install_fltr_rule_resp_ex_msg_v01 { 467 struct ipa_qmi_response_type_v01 resp; 468 uint8_t rule_id_valid; 469 uint32_t rule_id_len; 470 uint32_t rule_id[QMI_IPA_MAX_FILTERS_EX_V01]; 471 }; 472 struct ipa_enable_per_client_stats_req_msg_v01 { 473 uint8_t enable_per_client_stats; 474 }; 475 struct ipa_enable_per_client_stats_resp_msg_v01 { 476 struct ipa_qmi_response_type_v01 resp; 477 }; 478 struct ipa_per_client_stats_info_type_v01 { 479 uint32_t client_id; 480 uint32_t src_pipe_id; 481 uint64_t num_ul_ipv4_bytes; 482 uint64_t num_ul_ipv6_bytes; 483 uint64_t num_dl_ipv4_bytes; 484 uint64_t num_dl_ipv6_bytes; 485 uint32_t num_ul_ipv4_pkts; 486 uint32_t num_ul_ipv6_pkts; 487 uint32_t num_dl_ipv4_pkts; 488 uint32_t num_dl_ipv6_pkts; 489 }; 490 struct ipa_get_stats_per_client_req_msg_v01 { 491 uint32_t client_id; 492 uint32_t src_pipe_id; 493 uint8_t reset_stats_valid; 494 uint8_t reset_stats; 495 }; 496 struct ipa_get_stats_per_client_resp_msg_v01 { 497 struct ipa_qmi_response_type_v01 resp; 498 uint8_t per_client_stats_list_valid; 499 uint32_t per_client_stats_list_len; 500 struct ipa_per_client_stats_info_type_v01 per_client_stats_list[QMI_IPA_MAX_PER_CLIENTS_V01]; 501 }; 502 struct ipa_ul_firewall_rule_type_v01 { 503 enum ipa_ip_type_enum_v01 ip_type; 504 struct ipa_filter_rule_type_v01 filter_rule; 505 }; 506 struct ipa_configure_ul_firewall_rules_req_msg_v01 { 507 uint32_t firewall_rules_list_len; 508 struct ipa_ul_firewall_rule_type_v01 firewall_rules_list[QMI_IPA_MAX_UL_FIREWALL_RULES_V01]; 509 uint32_t mux_id; 510 uint8_t disable_valid; 511 uint8_t disable; 512 uint8_t are_blacklist_filters_valid; 513 uint8_t are_blacklist_filters; 514 }; 515 struct ipa_configure_ul_firewall_rules_resp_msg_v01 { 516 struct ipa_qmi_response_type_v01 resp; 517 }; 518 enum ipa_ul_firewall_status_enum_v01 { 519 IPA_UL_FIREWALL_STATUS_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 520 QMI_IPA_UL_FIREWALL_STATUS_SUCCESS_V01 = 0, 521 QMI_IPA_UL_FIREWALL_STATUS_FAILURE_V01 = 1, 522 IPA_UL_FIREWALL_STATUS_ENUM_MAX_ENUM_VAL_V01 = 2147483647 523 }; 524 struct ipa_ul_firewall_config_result_type_v01 { 525 enum ipa_ul_firewall_status_enum_v01 is_success; 526 uint32_t mux_id; 527 }; 528 struct ipa_configure_ul_firewall_rules_ind_msg_v01 { 529 struct ipa_ul_firewall_config_result_type_v01 result; 530 }; 531 #define QMI_IPA_INDICATION_REGISTER_REQ_V01 0x0020 532 #define QMI_IPA_INDICATION_REGISTER_RESP_V01 0x0020 533 #define QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 0x0021 534 #define QMI_IPA_INIT_MODEM_DRIVER_RESP_V01 0x0021 535 #define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_V01 0x0022 536 #define QMI_IPA_INSTALL_FILTER_RULE_REQ_V01 0x0023 537 #define QMI_IPA_INSTALL_FILTER_RULE_RESP_V01 0x0023 538 #define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01 0x0024 539 #define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01 0x0024 540 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0025 541 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0025 542 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0026 543 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0026 544 #define QMI_IPA_CONFIG_REQ_V01 0x0027 545 #define QMI_IPA_CONFIG_RESP_V01 0x0027 546 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0028 547 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0028 548 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0029 549 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0029 550 #define QMI_IPA_GET_DATA_STATS_REQ_V01 0x0030 551 #define QMI_IPA_GET_DATA_STATS_RESP_V01 0x0030 552 #define QMI_IPA_GET_APN_DATA_STATS_REQ_V01 0x0031 553 #define QMI_IPA_GET_APN_DATA_STATS_RESP_V01 0x0031 554 #define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01 0x0032 555 #define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01 0x0032 556 #define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_V01 0x0033 557 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01 0x0034 558 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01 0x0034 559 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_V01 0x0035 560 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01 0x0035 561 #define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_V01 0x0037 562 #define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_V01 0x0037 563 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01 0x0038 564 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_V01 0x0038 565 #define QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01 0x0039 566 #define QMI_IPA_GET_STATS_PER_CLIENT_RESP_V01 0x0039 567 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_V01 0x003A 568 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_V01 0x003A 569 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_V01 0x003A 570 #define QMI_IPA_INIT_MODEM_DRIVER_REQ_MAX_MSG_LEN_V01 162 571 #define QMI_IPA_INIT_MODEM_DRIVER_RESP_MAX_MSG_LEN_V01 25 572 #define QMI_IPA_INDICATION_REGISTER_REQ_MAX_MSG_LEN_V01 8 573 #define QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01 7 574 #define QMI_IPA_INSTALL_FILTER_RULE_REQ_MAX_MSG_LEN_V01 22369 575 #define QMI_IPA_INSTALL_FILTER_RULE_RESP_MAX_MSG_LEN_V01 783 576 #define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_MAX_MSG_LEN_V01 870 577 #define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01 7 578 #define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_MAX_MSG_LEN_V01 7 579 #define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_MAX_MSG_LEN_V01 15 580 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 18 581 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 7 582 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 583 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 584 #define QMI_IPA_CONFIG_REQ_MAX_MSG_LEN_V01 102 585 #define QMI_IPA_CONFIG_RESP_MAX_MSG_LEN_V01 7 586 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 18 587 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 588 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 7 589 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 590 #define QMI_IPA_GET_DATA_STATS_REQ_MAX_MSG_LEN_V01 11 591 #define QMI_IPA_GET_DATA_STATS_RESP_MAX_MSG_LEN_V01 2234 592 #define QMI_IPA_GET_APN_DATA_STATS_REQ_MAX_MSG_LEN_V01 36 593 #define QMI_IPA_GET_APN_DATA_STATS_RESP_MAX_MSG_LEN_V01 299 594 #define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 100 595 #define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 596 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 0 597 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 598 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_MAX_MSG_LEN_V01 4 599 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_MAX_MSG_LEN_V01 7 600 #define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_MAX_MSG_LEN_V01 22685 601 #define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_MAX_MSG_LEN_V01 523 602 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_MAX_MSG_LEN_V01 4 603 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_MAX_MSG_LEN_V01 7 604 #define QMI_IPA_GET_STATS_PER_CLIENT_REQ_MAX_MSG_LEN_V01 18 605 #define QMI_IPA_GET_STATS_PER_CLIENT_RESP_MAX_MSG_LEN_V01 3595 606 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_MAX_MSG_LEN_V01 9875 607 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_MAX_MSG_LEN_V01 7 608 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_MAX_MSG_LEN_V01 11 609 #endif 610 611