1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_DRM_H__ 19 #define __MSM_DRM_H__ 20 21 #include "drm.h" 22 #include "sde_drm.h" 23 24 #if defined(__cplusplus) 25 extern "C" { 26 #endif 27 28 /* Please note that modifications to all structs defined here are 29 * subject to backwards-compatibility constraints: 30 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit 31 * user/kernel compatibility 32 * 2) Keep fields aligned to their size 33 * 3) Because of how drm_ioctl() works, we can add new fields at 34 * the end of an ioctl if some care is taken: drm_ioctl() will 35 * zero out the new fields at the tail of the ioctl, so a zero 36 * value should have a backwards compatible meaning. And for 37 * output params, userspace won't see the newly added output 38 * fields.. so that has to be somehow ok. 39 */ 40 41 #define MSM_PIPE_NONE 0x00 42 #define MSM_PIPE_2D0 0x01 43 #define MSM_PIPE_2D1 0x02 44 #define MSM_PIPE_3D0 0x10 45 46 /* The pipe-id just uses the lower bits, so can be OR'd with flags in 47 * the upper 16 bits (which could be extended further, if needed, maybe 48 * we extend/overload the pipe-id some day to deal with multiple rings, 49 * but even then I don't think we need the full lower 16 bits). 50 */ 51 #define MSM_PIPE_ID_MASK 0xffff 52 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 53 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 54 55 /* timeouts are specified in clock-monotonic absolute times (to simplify 56 * restarting interrupted ioctls). The following struct is logically the 57 * same as 'struct timespec' but 32/64b ABI safe. 58 */ 59 struct drm_msm_timespec { 60 __s64 tv_sec; /* seconds */ 61 __s64 tv_nsec; /* nanoseconds */ 62 }; 63 64 /* 65 * HDR Metadata 66 * These are defined as per EDID spec and shall be used by the sink 67 * to set the HDR metadata for playback from userspace. 68 */ 69 70 #define HDR_PRIMARIES_COUNT 3 71 72 /* HDR EOTF */ 73 #define HDR_EOTF_SDR_LUM_RANGE 0x0 74 #define HDR_EOTF_HDR_LUM_RANGE 0x1 75 #define HDR_EOTF_SMTPE_ST2084 0x2 76 #define HDR_EOTF_HLG 0x3 77 78 #define DRM_MSM_EXT_HDR_METADATA 79 struct drm_msm_ext_hdr_metadata { 80 __u32 hdr_state; /* HDR state */ 81 __u32 eotf; /* electro optical transfer function */ 82 __u32 hdr_supported; /* HDR supported */ 83 __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; /* Primaries x */ 84 __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; /* Primaries y */ 85 __u32 white_point_x; /* white_point_x */ 86 __u32 white_point_y; /* white_point_y */ 87 __u32 max_luminance; /* Max luminance */ 88 __u32 min_luminance; /* Min Luminance */ 89 __u32 max_content_light_level; /* max content light level */ 90 __u32 max_average_light_level; /* max average light level */ 91 }; 92 93 /** 94 * HDR sink properties 95 * These are defined as per EDID spec and shall be used by the userspace 96 * to determine the HDR properties to be set to the sink. 97 */ 98 #define DRM_MSM_EXT_HDR_PROPERTIES 99 struct drm_msm_ext_hdr_properties { 100 __u8 hdr_metadata_type_one; /* static metadata type one */ 101 __u32 hdr_supported; /* HDR supported */ 102 __u32 hdr_eotf; /* electro optical transfer function */ 103 __u32 hdr_max_luminance; /* Max luminance */ 104 __u32 hdr_avg_luminance; /* Avg luminance */ 105 __u32 hdr_min_luminance; /* Min Luminance */ 106 }; 107 108 #define MSM_PARAM_GPU_ID 0x01 109 #define MSM_PARAM_GMEM_SIZE 0x02 110 #define MSM_PARAM_CHIP_ID 0x03 111 #define MSM_PARAM_MAX_FREQ 0x04 112 #define MSM_PARAM_TIMESTAMP 0x05 113 114 struct drm_msm_param { 115 __u32 pipe; /* in, MSM_PIPE_x */ 116 __u32 param; /* in, MSM_PARAM_x */ 117 __u64 value; /* out (get_param) or in (set_param) */ 118 }; 119 120 /* 121 * GEM buffers: 122 */ 123 124 #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ 125 #define MSM_BO_GPU_READONLY 0x00000002 126 #define MSM_BO_CACHE_MASK 0x000f0000 127 /* cache modes */ 128 #define MSM_BO_CACHED 0x00010000 129 #define MSM_BO_WC 0x00020000 130 #define MSM_BO_UNCACHED 0x00040000 131 132 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ 133 MSM_BO_GPU_READONLY | \ 134 MSM_BO_CACHED | \ 135 MSM_BO_WC | \ 136 MSM_BO_UNCACHED) 137 138 struct drm_msm_gem_new { 139 __u64 size; /* in */ 140 __u32 flags; /* in, mask of MSM_BO_x */ 141 __u32 handle; /* out */ 142 }; 143 144 struct drm_msm_gem_info { 145 __u32 handle; /* in */ 146 __u32 pad; 147 __u64 offset; /* out, offset to pass to mmap() */ 148 }; 149 150 #define MSM_PREP_READ 0x01 151 #define MSM_PREP_WRITE 0x02 152 #define MSM_PREP_NOSYNC 0x04 153 154 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 155 156 struct drm_msm_gem_cpu_prep { 157 __u32 handle; /* in */ 158 __u32 op; /* in, mask of MSM_PREP_x */ 159 struct drm_msm_timespec timeout; /* in */ 160 }; 161 162 struct drm_msm_gem_cpu_fini { 163 __u32 handle; /* in */ 164 }; 165 166 /* 167 * Cmdstream Submission: 168 */ 169 170 /* The value written into the cmdstream is logically: 171 * 172 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or 173 * 174 * When we have GPU's w/ >32bit ptrs, it should be possible to deal 175 * with this by emit'ing two reloc entries with appropriate shift 176 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. 177 * 178 * NOTE that reloc's must be sorted by order of increasing submit_offset, 179 * otherwise EINVAL. 180 */ 181 struct drm_msm_gem_submit_reloc { 182 __u32 submit_offset; /* in, offset from submit_bo */ 183 __u32 or; /* in, value OR'd with result */ 184 __s32 shift; /* in, amount of left shift (can be negative) */ 185 __u32 reloc_idx; /* in, index of reloc_bo buffer */ 186 __u64 reloc_offset; /* in, offset from start of reloc_bo */ 187 }; 188 189 /* submit-types: 190 * BUF - this cmd buffer is executed normally. 191 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are 192 * processed normally, but the kernel does not setup an IB to 193 * this buffer in the first-level ringbuffer 194 * CTX_RESTORE_BUF - only executed if there has been a GPU context 195 * switch since the last SUBMIT ioctl 196 */ 197 #define MSM_SUBMIT_CMD_BUF 0x0001 198 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 199 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 200 struct drm_msm_gem_submit_cmd { 201 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */ 202 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */ 203 __u32 submit_offset; /* in, offset into submit_bo */ 204 __u32 size; /* in, cmdstream size */ 205 __u32 pad; 206 __u32 nr_relocs; /* in, number of submit_reloc's */ 207 __u64 relocs; /* in, ptr to array of submit_reloc's */ 208 }; 209 210 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the 211 * cmdstream buffer(s) themselves or reloc entries) has one (and only 212 * one) entry in the submit->bos[] table. 213 * 214 * As a optimization, the current buffer (gpu virtual address) can be 215 * passed back through the 'presumed' field. If on a subsequent reloc, 216 * userspace passes back a 'presumed' address that is still valid, 217 * then patching the cmdstream for this entry is skipped. This can 218 * avoid kernel needing to map/access the cmdstream bo in the common 219 * case. 220 */ 221 #define MSM_SUBMIT_BO_READ 0x0001 222 #define MSM_SUBMIT_BO_WRITE 0x0002 223 224 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 225 226 struct drm_msm_gem_submit_bo { 227 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */ 228 __u32 handle; /* in, GEM handle */ 229 __u64 presumed; /* in/out, presumed buffer address */ 230 }; 231 232 /* Valid submit ioctl flags: */ 233 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */ 234 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */ 235 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */ 236 #define MSM_SUBMIT_FLAGS ( \ 237 MSM_SUBMIT_NO_IMPLICIT | \ 238 MSM_SUBMIT_FENCE_FD_IN | \ 239 MSM_SUBMIT_FENCE_FD_OUT | \ 240 0) 241 242 /* Each cmdstream submit consists of a table of buffers involved, and 243 * one or more cmdstream buffers. This allows for conditional execution 244 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 245 */ 246 struct drm_msm_gem_submit { 247 __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ 248 __u32 fence; /* out */ 249 __u32 nr_bos; /* in, number of submit_bo's */ 250 __u32 nr_cmds; /* in, number of submit_cmd's */ 251 __u64 bos; /* in, ptr to array of submit_bo's */ 252 __u64 cmds; /* in, ptr to array of submit_cmd's */ 253 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ 254 }; 255 256 /* The normal way to synchronize with the GPU is just to CPU_PREP on 257 * a buffer if you need to access it from the CPU (other cmdstream 258 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all 259 * handle the required synchronization under the hood). This ioctl 260 * mainly just exists as a way to implement the gallium pipe_fence 261 * APIs without requiring a dummy bo to synchronize on. 262 */ 263 struct drm_msm_wait_fence { 264 __u32 fence; /* in */ 265 __u32 pad; 266 struct drm_msm_timespec timeout; /* in */ 267 }; 268 269 /* madvise provides a way to tell the kernel in case a buffers contents 270 * can be discarded under memory pressure, which is useful for userspace 271 * bo cache where we want to optimistically hold on to buffer allocate 272 * and potential mmap, but allow the pages to be discarded under memory 273 * pressure. 274 * 275 * Typical usage would involve madvise(DONTNEED) when buffer enters BO 276 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. 277 * In the WILLNEED case, 'retained' indicates to userspace whether the 278 * backing pages still exist. 279 */ 280 #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ 281 #define MSM_MADV_DONTNEED 1 /* backing pages not needed */ 282 #define __MSM_MADV_PURGED 2 /* internal state */ 283 284 struct drm_msm_gem_madvise { 285 __u32 handle; /* in, GEM handle */ 286 __u32 madv; /* in, MSM_MADV_x */ 287 __u32 retained; /* out, whether backing store still exists */ 288 }; 289 290 /* HDR WRGB x and y index */ 291 #define DISPLAY_PRIMARIES_WX 0 292 #define DISPLAY_PRIMARIES_WY 1 293 #define DISPLAY_PRIMARIES_RX 2 294 #define DISPLAY_PRIMARIES_RY 3 295 #define DISPLAY_PRIMARIES_GX 4 296 #define DISPLAY_PRIMARIES_GY 5 297 #define DISPLAY_PRIMARIES_BX 6 298 #define DISPLAY_PRIMARIES_BY 7 299 #define DISPLAY_PRIMARIES_MAX 8 300 301 struct drm_panel_hdr_properties { 302 __u32 hdr_enabled; 303 304 /* WRGB X and y values arrayed in format */ 305 /* [WX, WY, RX, RY, GX, GY, BX, BY] */ 306 __u32 display_primaries[DISPLAY_PRIMARIES_MAX]; 307 308 /* peak brightness supported by panel */ 309 __u32 peak_brightness; 310 /* Blackness level supported by panel */ 311 __u32 blackness_level; 312 }; 313 314 /** 315 * struct drm_msm_event_req - Payload to event enable/disable ioctls. 316 * @object_id: DRM object id. e.g.: for crtc pass crtc id. 317 * @object_type: DRM object type. e.g.: for crtc set it to DRM_MODE_OBJECT_CRTC. 318 * @event: Event for which notification is being enabled/disabled. 319 * e.g.: for Histogram set - DRM_EVENT_HISTOGRAM. 320 * @client_context: Opaque pointer that will be returned during event response 321 * notification. 322 * @index: Object index(e.g.: crtc index), optional for user-space to set. 323 * Driver will override value based on object_id and object_type. 324 */ 325 struct drm_msm_event_req { 326 __u32 object_id; 327 __u32 object_type; 328 __u32 event; 329 __u64 client_context; 330 __u32 index; 331 }; 332 333 /** 334 * struct drm_msm_event_resp - payload returned when read is called for 335 * custom notifications. 336 * @base: Event type and length of complete notification payload. 337 * @info: Contains information about DRM that which raised this event. 338 * @data: Custom payload that driver returns for event type. 339 * size of data = base.length - (sizeof(base) + sizeof(info)) 340 */ 341 struct drm_msm_event_resp { 342 struct drm_event base; 343 struct drm_msm_event_req info; 344 __u8 data[]; 345 }; 346 347 #define DRM_MSM_GET_PARAM 0x00 348 /* placeholder: 349 #define DRM_MSM_SET_PARAM 0x01 350 */ 351 #define DRM_MSM_GEM_NEW 0x02 352 #define DRM_MSM_GEM_INFO 0x03 353 #define DRM_MSM_GEM_CPU_PREP 0x04 354 #define DRM_MSM_GEM_CPU_FINI 0x05 355 #define DRM_MSM_GEM_SUBMIT 0x06 356 #define DRM_MSM_WAIT_FENCE 0x07 357 #define DRM_MSM_GEM_MADVISE 0x08 358 359 #define DRM_SDE_WB_CONFIG 0x40 360 #define DRM_MSM_REGISTER_EVENT 0x41 361 #define DRM_MSM_DEREGISTER_EVENT 0x42 362 #define DRM_MSM_RMFB2 0x43 363 364 /* sde custom events */ 365 #define DRM_EVENT_HISTOGRAM 0x80000000 366 #define DRM_EVENT_AD_BACKLIGHT 0x80000001 367 #define DRM_EVENT_CRTC_POWER 0x80000002 368 #define DRM_EVENT_SYS_BACKLIGHT 0x80000003 369 #define DRM_EVENT_SDE_POWER 0x80000004 370 #define DRM_EVENT_IDLE_NOTIFY 0x80000005 371 #define DRM_EVENT_PANEL_DEAD 0x80000006 /* ESD event */ 372 373 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 374 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 375 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 376 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 377 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 378 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 379 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 380 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 381 #define DRM_IOCTL_SDE_WB_CONFIG \ 382 DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) 383 #define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ 384 DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) 385 #define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ 386 DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) 387 #define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + \ 388 DRM_MSM_RMFB2), unsigned int) 389 390 #if defined(__cplusplus) 391 } 392 #endif 393 394 #endif /* __MSM_DRM_H__ */ 395