1 #ifndef _MSM_MDP_H_ 2 #define _MSM_MDP_H_ 3 4 #include <stdint.h> 5 #include <linux/fb.h> 6 7 #define MSMFB_IOCTL_MAGIC 'm' 8 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 9 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 10 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 11 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 12 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 13 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 14 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 15 /* new ioctls's for set/get ccs matrix */ 16 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 17 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 18 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 19 struct mdp_overlay) 20 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 21 22 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 23 struct msmfb_overlay_data) 24 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 26 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 27 struct mdp_page_protection) 28 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 29 struct mdp_page_protection) 30 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 31 struct mdp_overlay) 32 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 33 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 34 struct msmfb_overlay_blt) 35 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 36 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 37 struct mdp_histogram_start_req) 38 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 39 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 40 41 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 42 struct msmfb_overlay_3d) 43 44 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 45 struct msmfb_mixer_info_req) 46 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 47 struct msmfb_overlay_data) 48 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 49 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 50 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 51 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 52 struct msmfb_data) 53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 54 struct msmfb_data) 55 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 56 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 57 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 58 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 59 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 60 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 61 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 62 struct mdp_display_commit) 63 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 64 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 65 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 66 unsigned int) 67 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 68 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 69 struct mdp_overlay_list) 70 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 71 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \ 72 struct mdp_pp_feature_version) 73 74 #define FB_TYPE_3D_PANEL 0x10101010 75 #define MDP_IMGTYPE2_START 0x10000 76 #define MSMFB_DRIVER_VERSION 0xF9E8D701 77 /* Maximum number of formats supported by MDP*/ 78 #define MDP_IMGTYPE_END 0x100 79 80 /* HW Revisions for different MDSS targets */ 81 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 82 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 83 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 84 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 85 86 #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 87 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 88 89 #define MDSS_MDP_REV(major, minor, step) \ 90 ((((major) & 0x000F) << 28) | \ 91 (((minor) & 0x0FFF) << 16) | \ 92 ((step) & 0xFFFF)) 93 94 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 95 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 96 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 97 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 98 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 99 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 100 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 101 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 102 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ 103 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ 104 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */ 105 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */ 106 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */ 107 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ 108 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ 109 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ 110 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 111 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */ 112 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */ 113 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) /* msmgold */ 114 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ 115 #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msmcobalt */ 116 #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msmcobalt v1.0 */ 117 118 enum { 119 NOTIFY_UPDATE_INIT, 120 NOTIFY_UPDATE_DEINIT, 121 NOTIFY_UPDATE_START, 122 NOTIFY_UPDATE_STOP, 123 NOTIFY_UPDATE_POWER_OFF, 124 }; 125 126 enum { 127 NOTIFY_TYPE_NO_UPDATE, 128 NOTIFY_TYPE_SUSPEND, 129 NOTIFY_TYPE_UPDATE, 130 NOTIFY_TYPE_BL_UPDATE, 131 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 132 }; 133 134 enum { 135 MDP_RGB_565, /* RGB 565 planer */ 136 MDP_XRGB_8888, /* RGB 888 padded */ 137 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 138 MDP_Y_CBCR_H2V2_ADRENO, 139 MDP_ARGB_8888, /* ARGB 888 */ 140 MDP_RGB_888, /* RGB 888 planer */ 141 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 142 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 143 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 144 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 145 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 146 MDP_Y_CRCB_H1V2, 147 MDP_Y_CBCR_H1V2, 148 MDP_RGBA_8888, /* ARGB 888 */ 149 MDP_BGRA_8888, /* ABGR 888 */ 150 MDP_RGBX_8888, /* RGBX 888 */ 151 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 152 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 153 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 154 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 155 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 156 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 157 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 158 MDP_YCRCB_H1V1, /* YCrCb interleave */ 159 MDP_YCBCR_H1V1, /* YCbCr interleave */ 160 MDP_BGR_565, /* BGR 565 planer */ 161 MDP_BGR_888, /* BGR 888 */ 162 MDP_Y_CBCR_H2V2_VENUS, 163 MDP_BGRX_8888, /* BGRX 8888 */ 164 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 165 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 166 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 167 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 168 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 169 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 170 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 171 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 172 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 173 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 174 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 175 MDP_ARGB_1555, /*ARGB 1555*/ 176 MDP_RGBA_5551, /*RGBA 5551*/ 177 MDP_ARGB_4444, /*ARGB 4444*/ 178 MDP_RGBA_4444, /*RGBA 4444*/ 179 MDP_RGB_565_UBWC, 180 MDP_RGBA_8888_UBWC, 181 MDP_Y_CBCR_H2V2_UBWC, 182 MDP_RGBX_8888_UBWC, 183 MDP_Y_CRCB_H2V2_VENUS, 184 MDP_IMGTYPE_LIMIT, 185 MDP_RGB_BORDERFILL, /* border fill pipe */ 186 MDP_XRGB_1555, 187 MDP_RGBX_5551, 188 MDP_XRGB_4444, 189 MDP_RGBX_4444, 190 MDP_ABGR_1555, 191 MDP_BGRA_5551, 192 MDP_XBGR_1555, 193 MDP_BGRX_5551, 194 MDP_ABGR_4444, 195 MDP_BGRA_4444, 196 MDP_XBGR_4444, 197 MDP_BGRX_4444, 198 MDP_ABGR_8888, 199 MDP_XBGR_8888, 200 MDP_RGBA_1010102, 201 MDP_ARGB_2101010, 202 MDP_RGBX_1010102, 203 MDP_XRGB_2101010, 204 MDP_BGRA_1010102, 205 MDP_ABGR_2101010, 206 MDP_BGRX_1010102, 207 MDP_XBGR_2101010, 208 MDP_RGBA_1010102_UBWC, 209 MDP_RGBX_1010102_UBWC, 210 MDP_Y_CBCR_H2V2_P010, 211 MDP_Y_CBCR_H2V2_TP10_UBWC, 212 MDP_CRYCBY_H2V1, /* CrYCbY interleave */ 213 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 214 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 215 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 216 }; 217 218 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 219 220 enum { 221 PMEM_IMG, 222 FB_IMG, 223 }; 224 225 enum { 226 HSIC_HUE = 0, 227 HSIC_SAT, 228 HSIC_INT, 229 HSIC_CON, 230 NUM_HSIC_PARAM, 231 }; 232 233 enum mdss_mdp_max_bw_mode { 234 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 235 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 236 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 237 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 238 }; 239 240 #define MDSS_MDP_ROT_ONLY 0x80 241 #define MDSS_MDP_RIGHT_MIXER 0x100 242 #define MDSS_MDP_DUAL_PIPE 0x200 243 244 /* mdp_blit_req flag values */ 245 #define MDP_ROT_NOP 0 246 #define MDP_FLIP_LR 0x1 247 #define MDP_FLIP_UD 0x2 248 #define MDP_ROT_90 0x4 249 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 250 #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 251 #define MDP_DITHER 0x8 252 #define MDP_BLUR 0x10 253 #define MDP_BLEND_FG_PREMULT 0x20000 254 #define MDP_IS_FG 0x40000 255 #define MDP_SOLID_FILL 0x00000020 256 #define MDP_VPU_PIPE 0x00000040 257 #define MDP_DEINTERLACE 0x80000000 258 #define MDP_SHARPENING 0x40000000 259 #define MDP_NO_DMA_BARRIER_START 0x20000000 260 #define MDP_NO_DMA_BARRIER_END 0x10000000 261 #define MDP_NO_BLIT 0x08000000 262 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 263 #define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 264 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 265 #define MDP_BLIT_SRC_GEM 0x04000000 266 #define MDP_BLIT_DST_GEM 0x02000000 267 #define MDP_BLIT_NON_CACHED 0x01000000 268 #define MDP_OV_PIPE_SHARE 0x00800000 269 #define MDP_DEINTERLACE_ODD 0x00400000 270 #define MDP_OV_PLAY_NOWAIT 0x00200000 271 #define MDP_SOURCE_ROTATED_90 0x00100000 272 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 273 #define MDP_BACKEND_COMPOSITION 0x00040000 274 #define MDP_BORDERFILL_SUPPORTED 0x00010000 275 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 276 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 277 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 278 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 279 #define MDP_BWC_EN 0x00000400 280 #define MDP_DECIMATION_EN 0x00000800 281 #define MDP_SMP_FORCE_ALLOC 0x00200000 282 #define MDP_TRANSP_NOP 0xffffffff 283 #define MDP_ALPHA_NOP 0xff 284 285 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 286 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 287 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 288 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 289 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 290 /* Sentinel: Don't use! */ 291 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 292 /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 293 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 294 295 #define MDP_DEEP_COLOR_YUV444 0x1 296 #define MDP_DEEP_COLOR_RGB30B 0x2 297 #define MDP_DEEP_COLOR_RGB36B 0x4 298 #define MDP_DEEP_COLOR_RGB48B 0x8 299 300 struct mdp_rect { 301 uint32_t x; 302 uint32_t y; 303 uint32_t w; 304 uint32_t h; 305 }; 306 307 struct mdp_img { 308 uint32_t width; 309 uint32_t height; 310 uint32_t format; 311 uint32_t offset; 312 int memory_id; /* the file descriptor */ 313 uint32_t priv; 314 }; 315 316 struct mult_factor { 317 uint32_t numer; 318 uint32_t denom; 319 }; 320 321 /* 322 * {3x3} + {3} ccs matrix 323 */ 324 325 #define MDP_CCS_RGB2YUV 0 326 #define MDP_CCS_YUV2RGB 1 327 328 #define MDP_CCS_SIZE 9 329 #define MDP_BV_SIZE 3 330 331 struct mdp_ccs { 332 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 333 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 334 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 335 }; 336 337 struct mdp_csc { 338 int id; 339 uint32_t csc_mv[9]; 340 uint32_t csc_pre_bv[3]; 341 uint32_t csc_post_bv[3]; 342 uint32_t csc_pre_lv[6]; 343 uint32_t csc_post_lv[6]; 344 }; 345 346 /* The version of the mdp_blit_req structure so that 347 * user applications can selectively decide which functionality 348 * to include 349 */ 350 351 #define MDP_BLIT_REQ_VERSION 3 352 353 struct color { 354 uint32_t r; 355 uint32_t g; 356 uint32_t b; 357 uint32_t alpha; 358 }; 359 360 struct mdp_blit_req { 361 struct mdp_img src; 362 struct mdp_img dst; 363 struct mdp_rect src_rect; 364 struct mdp_rect dst_rect; 365 struct color const_color; 366 uint32_t alpha; 367 uint32_t transp_mask; 368 uint32_t flags; 369 int sharpening_strength; /* -127 <--> 127, default 64 */ 370 uint8_t color_space; 371 uint32_t fps; 372 }; 373 374 struct mdp_blit_req_list { 375 uint32_t count; 376 struct mdp_blit_req req[]; 377 }; 378 379 #define MSMFB_DATA_VERSION 2 380 381 struct msmfb_data { 382 uint32_t offset; 383 int memory_id; 384 int id; 385 uint32_t flags; 386 uint32_t priv; 387 uint32_t iova; 388 }; 389 390 #define MSMFB_NEW_REQUEST -1 391 392 struct msmfb_overlay_data { 393 uint32_t id; 394 struct msmfb_data data; 395 uint32_t version_key; 396 struct msmfb_data plane1_data; 397 struct msmfb_data plane2_data; 398 struct msmfb_data dst_data; 399 }; 400 401 struct msmfb_img { 402 uint32_t width; 403 uint32_t height; 404 uint32_t format; 405 }; 406 407 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 408 struct msmfb_writeback_data { 409 struct msmfb_data buf_info; 410 struct msmfb_img img; 411 }; 412 413 #define MDP_PP_OPS_ENABLE 0x1 414 #define MDP_PP_OPS_READ 0x2 415 #define MDP_PP_OPS_WRITE 0x4 416 #define MDP_PP_OPS_DISABLE 0x8 417 #define MDP_PP_IGC_FLAG_ROM0 0x10 418 #define MDP_PP_IGC_FLAG_ROM1 0x20 419 420 421 #define MDSS_PP_DSPP_CFG 0x000 422 #define MDSS_PP_SSPP_CFG 0x100 423 #define MDSS_PP_LM_CFG 0x200 424 #define MDSS_PP_WB_CFG 0x300 425 426 #define MDSS_PP_ARG_MASK 0x3C00 427 #define MDSS_PP_ARG_NUM 4 428 #define MDSS_PP_ARG_SHIFT 10 429 #define MDSS_PP_LOCATION_MASK 0x0300 430 #define MDSS_PP_LOGICAL_MASK 0x00FF 431 432 #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 433 #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 434 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 435 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 436 437 438 struct mdp_qseed_cfg { 439 uint32_t table_num; 440 uint32_t ops; 441 uint32_t len; 442 uint32_t *data; 443 }; 444 445 struct mdp_sharp_cfg { 446 uint32_t flags; 447 uint32_t strength; 448 uint32_t edge_thr; 449 uint32_t smooth_thr; 450 uint32_t noise_thr; 451 }; 452 453 struct mdp_qseed_cfg_data { 454 uint32_t block; 455 struct mdp_qseed_cfg qseed_data; 456 }; 457 458 #define MDP_OVERLAY_PP_CSC_CFG 0x1 459 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 460 #define MDP_OVERLAY_PP_PA_CFG 0x4 461 #define MDP_OVERLAY_PP_IGC_CFG 0x8 462 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 463 #define MDP_OVERLAY_PP_HIST_CFG 0x20 464 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 465 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 466 #define MDP_OVERLAY_PP_PCC_CFG 0x100 467 468 #define MDP_CSC_FLAG_ENABLE 0x1 469 #define MDP_CSC_FLAG_YUV_IN 0x2 470 #define MDP_CSC_FLAG_YUV_OUT 0x4 471 472 #define MDP_CSC_MATRIX_COEFF_SIZE 9 473 #define MDP_CSC_CLAMP_SIZE 6 474 #define MDP_CSC_BIAS_SIZE 3 475 476 struct mdp_csc_cfg { 477 /* flags for enable CSC, toggling RGB,YUV input/output */ 478 uint32_t flags; 479 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 480 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 481 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 482 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 483 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 484 }; 485 486 struct mdp_csc_cfg_data { 487 uint32_t block; 488 struct mdp_csc_cfg csc_data; 489 }; 490 491 struct mdp_pa_cfg { 492 uint32_t flags; 493 uint32_t hue_adj; 494 uint32_t sat_adj; 495 uint32_t val_adj; 496 uint32_t cont_adj; 497 }; 498 499 struct mdp_pa_mem_col_cfg { 500 uint32_t color_adjust_p0; 501 uint32_t color_adjust_p1; 502 uint32_t hue_region; 503 uint32_t sat_region; 504 uint32_t val_region; 505 }; 506 507 #define MDP_SIX_ZONE_LUT_SIZE 384 508 509 /* PA Write/Read extension flags */ 510 #define MDP_PP_PA_HUE_ENABLE 0x10 511 #define MDP_PP_PA_SAT_ENABLE 0x20 512 #define MDP_PP_PA_VAL_ENABLE 0x40 513 #define MDP_PP_PA_CONT_ENABLE 0x80 514 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 515 #define MDP_PP_PA_SKIN_ENABLE 0x200 516 #define MDP_PP_PA_SKY_ENABLE 0x400 517 #define MDP_PP_PA_FOL_ENABLE 0x800 518 519 /* PA masks */ 520 /* Masks used in PA v1_7 only */ 521 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 522 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 523 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 524 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 525 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 526 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 527 /* Masks used in all PAv2 versions */ 528 #define MDP_PP_PA_HUE_MASK 0x1000 529 #define MDP_PP_PA_SAT_MASK 0x2000 530 #define MDP_PP_PA_VAL_MASK 0x4000 531 #define MDP_PP_PA_CONT_MASK 0x8000 532 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 533 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 534 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 535 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 536 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 537 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 538 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 539 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 540 541 /* Flags for setting PA saturation and value hold */ 542 #define MDP_PP_PA_LEFT_HOLD 0x1 543 #define MDP_PP_PA_RIGHT_HOLD 0x2 544 545 struct mdp_pa_v2_data { 546 /* Mask bits for PA features */ 547 uint32_t flags; 548 uint32_t global_hue_adj; 549 uint32_t global_sat_adj; 550 uint32_t global_val_adj; 551 uint32_t global_cont_adj; 552 struct mdp_pa_mem_col_cfg skin_cfg; 553 struct mdp_pa_mem_col_cfg sky_cfg; 554 struct mdp_pa_mem_col_cfg fol_cfg; 555 uint32_t six_zone_len; 556 uint32_t six_zone_thresh; 557 uint32_t *six_zone_curve_p0; 558 uint32_t *six_zone_curve_p1; 559 }; 560 561 struct mdp_pa_mem_col_data_v1_7 { 562 uint32_t color_adjust_p0; 563 uint32_t color_adjust_p1; 564 uint32_t color_adjust_p2; 565 uint32_t blend_gain; 566 uint8_t sat_hold; 567 uint8_t val_hold; 568 uint32_t hue_region; 569 uint32_t sat_region; 570 uint32_t val_region; 571 }; 572 573 struct mdp_pa_data_v1_7 { 574 uint32_t mode; 575 uint32_t global_hue_adj; 576 uint32_t global_sat_adj; 577 uint32_t global_val_adj; 578 uint32_t global_cont_adj; 579 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 580 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 581 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 582 uint32_t six_zone_thresh; 583 uint32_t six_zone_adj_p0; 584 uint32_t six_zone_adj_p1; 585 uint8_t six_zone_sat_hold; 586 uint8_t six_zone_val_hold; 587 uint32_t six_zone_len; 588 uint32_t *six_zone_curve_p0; 589 uint32_t *six_zone_curve_p1; 590 }; 591 592 593 struct mdp_pa_v2_cfg_data { 594 uint32_t version; 595 uint32_t block; 596 uint32_t flags; 597 struct mdp_pa_v2_data pa_v2_data; 598 void *cfg_payload; 599 }; 600 601 602 enum { 603 mdp_igc_rec601 = 1, 604 mdp_igc_rec709, 605 mdp_igc_srgb, 606 mdp_igc_custom, 607 mdp_igc_rec_max, 608 }; 609 610 struct mdp_igc_lut_data { 611 uint32_t block; 612 uint32_t version; 613 uint32_t len, ops; 614 uint32_t *c0_c1_data; 615 uint32_t *c2_data; 616 void *cfg_payload; 617 }; 618 619 struct mdp_igc_lut_data_v1_7 { 620 uint32_t table_fmt; 621 uint32_t len; 622 uint32_t *c0_c1_data; 623 uint32_t *c2_data; 624 }; 625 626 struct mdp_igc_lut_data_payload { 627 uint32_t table_fmt; 628 uint32_t len; 629 uint64_t c0_c1_data; 630 uint64_t c2_data; 631 uint32_t strength; 632 }; 633 634 struct mdp_histogram_cfg { 635 uint32_t ops; 636 uint32_t block; 637 uint8_t frame_cnt; 638 uint8_t bit_mask; 639 uint16_t num_bins; 640 }; 641 642 struct mdp_hist_lut_data_v1_7 { 643 uint32_t len; 644 uint32_t *data; 645 }; 646 647 struct mdp_hist_lut_data { 648 uint32_t block; 649 uint32_t version; 650 uint32_t hist_lut_first; 651 uint32_t ops; 652 uint32_t len; 653 uint32_t *data; 654 void *cfg_payload; 655 }; 656 657 struct mdp_pcc_coeff { 658 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 659 }; 660 661 struct mdp_pcc_coeff_v1_7 { 662 uint32_t c, r, g, b, rg, gb, rb, rgb; 663 }; 664 665 struct mdp_pcc_data_v1_7 { 666 struct mdp_pcc_coeff_v1_7 r, g, b; 667 }; 668 669 struct mdp_pcc_cfg_data { 670 uint32_t version; 671 uint32_t block; 672 uint32_t ops; 673 struct mdp_pcc_coeff r, g, b; 674 void *cfg_payload; 675 }; 676 677 enum { 678 mdp_lut_igc, 679 mdp_lut_pgc, 680 mdp_lut_hist, 681 mdp_lut_rgb, 682 mdp_lut_max, 683 }; 684 struct mdp_overlay_pp_params { 685 uint32_t config_ops; 686 struct mdp_csc_cfg csc_cfg; 687 struct mdp_qseed_cfg qseed_cfg[2]; 688 struct mdp_pa_cfg pa_cfg; 689 struct mdp_pa_v2_data pa_v2_cfg; 690 struct mdp_igc_lut_data igc_cfg; 691 struct mdp_sharp_cfg sharp_cfg; 692 struct mdp_histogram_cfg hist_cfg; 693 struct mdp_hist_lut_data hist_lut_cfg; 694 /* PAv2 cfg data for PA 2.x versions */ 695 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 696 struct mdp_pcc_cfg_data pcc_cfg_data; 697 }; 698 699 /** 700 * enum mdss_mdp_blend_op - Different blend operations set by userspace 701 * 702 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 703 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 704 * would appear opaque in case fg plane alpha is 705 * 0xff. 706 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 707 * alpha pre-multiplication done. If fg plane alpha 708 * is less than 0xff, apply modulation as well. This 709 * operation is intended on layers having alpha 710 * channel. 711 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 712 * pre-multiplied. Apply pre-multiplication. If fg 713 * plane alpha is less than 0xff, apply modulation as 714 * well. 715 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 716 * mdp. 717 */ 718 enum mdss_mdp_blend_op { 719 BLEND_OP_NOT_DEFINED = 0, 720 BLEND_OP_OPAQUE, 721 BLEND_OP_PREMULTIPLIED, 722 BLEND_OP_COVERAGE, 723 BLEND_OP_MAX, 724 }; 725 726 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 727 #define MAX_PLANES 4 728 struct mdp_scale_data { 729 uint8_t enable_pxl_ext; 730 731 int init_phase_x[MAX_PLANES]; 732 int phase_step_x[MAX_PLANES]; 733 int init_phase_y[MAX_PLANES]; 734 int phase_step_y[MAX_PLANES]; 735 736 int num_ext_pxls_left[MAX_PLANES]; 737 int num_ext_pxls_right[MAX_PLANES]; 738 int num_ext_pxls_top[MAX_PLANES]; 739 int num_ext_pxls_btm[MAX_PLANES]; 740 741 int left_ftch[MAX_PLANES]; 742 int left_rpt[MAX_PLANES]; 743 int right_ftch[MAX_PLANES]; 744 int right_rpt[MAX_PLANES]; 745 746 int top_rpt[MAX_PLANES]; 747 int btm_rpt[MAX_PLANES]; 748 int top_ftch[MAX_PLANES]; 749 int btm_ftch[MAX_PLANES]; 750 751 uint32_t roi_w[MAX_PLANES]; 752 }; 753 754 /** 755 * enum mdp_overlay_pipe_type - Different pipe type set by userspace 756 * 757 * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. 758 * @PIPE_TYPE_VIG: VIG pipe. 759 * @PIPE_TYPE_RGB: RGB pipe. 760 * @PIPE_TYPE_DMA: DMA pipe. 761 * @PIPE_TYPE_CURSOR: CURSOR pipe. 762 * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. 763 */ 764 enum mdp_overlay_pipe_type { 765 PIPE_TYPE_AUTO = 0, 766 PIPE_TYPE_VIG, 767 PIPE_TYPE_RGB, 768 PIPE_TYPE_DMA, 769 PIPE_TYPE_CURSOR, 770 PIPE_TYPE_MAX, 771 }; 772 773 /** 774 * struct mdp_overlay - overlay surface structure 775 * @src: Source image information (width, height, format). 776 * @src_rect: Source crop rectangle, portion of image that will be fetched. 777 * This should always be within boundaries of source image. 778 * @dst_rect: Destination rectangle, the position and size of image on screen. 779 * This should always be within panel boundaries. 780 * @z_order: Blending stage to occupy in display, if multiple layers are 781 * present, highest z_order usually means the top most visible 782 * layer. The range acceptable is from 0-3 to support blending 783 * up to 4 layers. 784 * @is_fg: This flag is used to disable blending of any layers with z_order 785 * less than this overlay. It means that any layers with z_order 786 * less than this layer will not be blended and will be replaced 787 * by the background border color. 788 * @alpha: Used to set plane opacity. The range can be from 0-255, where 789 * 0 means completely transparent and 255 means fully opaque. 790 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 791 * image matching this color will be transparent when blending. 792 * The color should be in same format as the source image format. 793 * @flags: This is used to customize operation of overlay. See MDP flags 794 * for more information. 795 * @pipe_type: Used to specify the type of overlay pipe. 796 * @user_data: DEPRECATED* Used to store user application specific information. 797 * @bg_color: Solid color used to fill the overlay surface when no source 798 * buffer is provided. 799 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 800 * dropped for each pixel that is fetched from a line. The value 801 * given should be power of two of decimation amount. 802 * 0: no decimation 803 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 804 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 805 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 806 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 807 * @vert_deci: Vertical decimation value, this indicates the amount of lines 808 * dropped for each line that is fetched from overlay. The value 809 * given should be power of two of decimation amount. 810 * 0: no decimation 811 * 1: decimation by 2 (drop 1 line for each line fetched) 812 * 2: decimation by 4 (drop 3 lines for each line fetched) 813 * 3: decimation by 8 (drop 7 lines for each line fetched) 814 * 4: decimation by 16 (drop 15 lines for each line fetched) 815 * @overlay_pp_cfg: Overlay post processing configuration, for more information 816 * see struct mdp_overlay_pp_params. 817 * @priority: Priority is returned by the driver when overlay is set for the 818 * first time. It indicates the priority of the underlying pipe 819 * serving the overlay. This priority can be used by user-space 820 * in source split when pipes are re-used and shuffled around to 821 * reduce fallbacks. 822 */ 823 struct mdp_overlay { 824 struct msmfb_img src; 825 struct mdp_rect src_rect; 826 struct mdp_rect dst_rect; 827 uint32_t z_order; /* stage number */ 828 uint32_t is_fg; /* control alpha & transp */ 829 uint32_t alpha; 830 uint32_t blend_op; 831 uint32_t transp_mask; 832 uint32_t flags; 833 uint32_t pipe_type; 834 uint32_t id; 835 uint8_t priority; 836 uint32_t user_data[6]; 837 uint32_t bg_color; 838 uint8_t horz_deci; 839 uint8_t vert_deci; 840 struct mdp_overlay_pp_params overlay_pp_cfg; 841 struct mdp_scale_data scale; 842 uint8_t color_space; 843 uint32_t frame_rate; 844 }; 845 846 struct msmfb_overlay_3d { 847 uint32_t is_3d; 848 uint32_t width; 849 uint32_t height; 850 }; 851 852 853 struct msmfb_overlay_blt { 854 uint32_t enable; 855 uint32_t offset; 856 uint32_t width; 857 uint32_t height; 858 uint32_t bpp; 859 }; 860 861 struct mdp_histogram { 862 uint32_t frame_cnt; 863 uint32_t bin_cnt; 864 uint32_t *r; 865 uint32_t *g; 866 uint32_t *b; 867 }; 868 869 #define MISR_CRC_BATCH_SIZE 32 870 enum { 871 DISPLAY_MISR_EDP, 872 DISPLAY_MISR_DSI0, 873 DISPLAY_MISR_DSI1, 874 DISPLAY_MISR_HDMI, 875 DISPLAY_MISR_LCDC, 876 DISPLAY_MISR_MDP, 877 DISPLAY_MISR_ATV, 878 DISPLAY_MISR_DSI_CMD, 879 DISPLAY_MISR_MAX 880 }; 881 882 enum { 883 MISR_OP_NONE, 884 MISR_OP_SFM, 885 MISR_OP_MFM, 886 MISR_OP_BM, 887 MISR_OP_MAX 888 }; 889 890 struct mdp_misr { 891 uint32_t block_id; 892 uint32_t frame_count; 893 uint32_t crc_op_mode; 894 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 895 }; 896 897 /* 898 * mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 899 * 900 * MDP_BLOCK_RESERVED is provided for backward compatibility and is 901 * deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 902 * instead. 903 * 904 * MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 905 * same for others. 906 */ 907 908 enum { 909 MDP_BLOCK_RESERVED = 0, 910 MDP_BLOCK_OVERLAY_0, 911 MDP_BLOCK_OVERLAY_1, 912 MDP_BLOCK_VG_1, 913 MDP_BLOCK_VG_2, 914 MDP_BLOCK_RGB_1, 915 MDP_BLOCK_RGB_2, 916 MDP_BLOCK_DMA_P, 917 MDP_BLOCK_DMA_S, 918 MDP_BLOCK_DMA_E, 919 MDP_BLOCK_OVERLAY_2, 920 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 921 MDP_LOGICAL_BLOCK_DISP_1, 922 MDP_LOGICAL_BLOCK_DISP_2, 923 MDP_BLOCK_MAX, 924 }; 925 926 /* 927 * mdp_histogram_start_req is used to provide the parameters for 928 * histogram start request 929 */ 930 931 struct mdp_histogram_start_req { 932 uint32_t block; 933 uint8_t frame_cnt; 934 uint8_t bit_mask; 935 uint16_t num_bins; 936 }; 937 938 /* 939 * mdp_histogram_data is used to return the histogram data, once 940 * the histogram is done/stopped/cance 941 */ 942 943 struct mdp_histogram_data { 944 uint32_t block; 945 uint32_t bin_cnt; 946 uint32_t *c0; 947 uint32_t *c1; 948 uint32_t *c2; 949 uint32_t *extra_info; 950 }; 951 952 953 #define GC_LUT_ENTRIES_V1_7 512 954 955 struct mdp_ar_gc_lut_data { 956 uint32_t x_start; 957 uint32_t slope; 958 uint32_t offset; 959 }; 960 961 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 962 struct mdp_pgc_lut_data { 963 uint32_t version; 964 uint32_t block; 965 uint32_t flags; 966 uint8_t num_r_stages; 967 uint8_t num_g_stages; 968 uint8_t num_b_stages; 969 struct mdp_ar_gc_lut_data *r_data; 970 struct mdp_ar_gc_lut_data *g_data; 971 struct mdp_ar_gc_lut_data *b_data; 972 void *cfg_payload; 973 }; 974 975 #define PGC_LUT_ENTRIES 1024 976 struct mdp_pgc_lut_data_v1_7 { 977 uint32_t len; 978 uint32_t *c0_data; 979 uint32_t *c1_data; 980 uint32_t *c2_data; 981 }; 982 983 /* 984 * mdp_rgb_lut_data is used to provide parameters for configuring the 985 * generic RGB lut in case of gamma correction or other LUT updation usecases 986 */ 987 struct mdp_rgb_lut_data { 988 uint32_t flags; 989 uint32_t lut_type; 990 struct fb_cmap cmap; 991 }; 992 993 enum { 994 mdp_rgb_lut_gc, 995 mdp_rgb_lut_hist, 996 }; 997 998 struct mdp_lut_cfg_data { 999 uint32_t lut_type; 1000 union { 1001 struct mdp_igc_lut_data igc_lut_data; 1002 struct mdp_pgc_lut_data pgc_lut_data; 1003 struct mdp_hist_lut_data hist_lut_data; 1004 struct mdp_rgb_lut_data rgb_lut_data; 1005 } data; 1006 }; 1007 1008 struct mdp_bl_scale_data { 1009 uint32_t min_lvl; 1010 uint32_t scale; 1011 }; 1012 1013 struct mdp_pa_cfg_data { 1014 uint32_t block; 1015 struct mdp_pa_cfg pa_data; 1016 }; 1017 1018 #define MDP_DITHER_DATA_V1_7_SZ 16 1019 1020 struct mdp_dither_data_v1_7 { 1021 uint32_t g_y_depth; 1022 uint32_t r_cr_depth; 1023 uint32_t b_cb_depth; 1024 uint32_t len; 1025 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 1026 uint32_t temporal_en; 1027 }; 1028 1029 struct mdp_pa_dither_data { 1030 uint64_t data_flags; 1031 uint32_t matrix_sz; 1032 uint64_t matrix_data; 1033 uint32_t strength; 1034 uint32_t offset_en; 1035 }; 1036 1037 struct mdp_dither_cfg_data { 1038 uint32_t version; 1039 uint32_t block; 1040 uint32_t flags; 1041 uint32_t mode; 1042 uint32_t g_y_depth; 1043 uint32_t r_cr_depth; 1044 uint32_t b_cb_depth; 1045 void *cfg_payload; 1046 }; 1047 1048 #define MDP_GAMUT_TABLE_NUM 8 1049 #define MDP_GAMUT_TABLE_NUM_V1_7 4 1050 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 1051 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 1052 #define MDP_GAMUT_SCALE_OFF_SZ 16 1053 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 1054 1055 struct mdp_gamut_cfg_data { 1056 uint32_t block; 1057 uint32_t flags; 1058 uint32_t version; 1059 /* v1 version specific params */ 1060 uint32_t gamut_first; 1061 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 1062 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 1063 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 1064 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 1065 /* params for newer versions of gamut */ 1066 void *cfg_payload; 1067 }; 1068 1069 enum { 1070 mdp_gamut_fine_mode = 0x1, 1071 mdp_gamut_coarse_mode, 1072 }; 1073 1074 struct mdp_gamut_data_v1_7 { 1075 uint32_t mode; 1076 uint32_t map_en; 1077 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 1078 uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1079 uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1080 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1081 uint32_t *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1082 }; 1083 1084 struct mdp_calib_config_data { 1085 uint32_t ops; 1086 uint32_t addr; 1087 uint32_t data; 1088 }; 1089 1090 struct mdp_calib_config_buffer { 1091 uint32_t ops; 1092 uint32_t size; 1093 uint32_t *buffer; 1094 }; 1095 1096 struct mdp_calib_dcm_state { 1097 uint32_t ops; 1098 uint32_t dcm_state; 1099 }; 1100 1101 enum { 1102 DCM_UNINIT, 1103 DCM_UNBLANK, 1104 DCM_ENTER, 1105 DCM_EXIT, 1106 DCM_BLANK, 1107 DTM_ENTER, 1108 DTM_EXIT, 1109 }; 1110 1111 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 1112 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 1113 #define MDSS_PP_SPLIT_MASK 0x30000000 1114 1115 #define MDSS_MAX_BL_BRIGHTNESS 255 1116 #define AD_BL_LIN_LEN 256 1117 #define AD_BL_ATT_LUT_LEN 33 1118 1119 #define MDSS_AD_MODE_AUTO_BL 0x0 1120 #define MDSS_AD_MODE_AUTO_STR 0x1 1121 #define MDSS_AD_MODE_TARG_STR 0x3 1122 #define MDSS_AD_MODE_MAN_STR 0x7 1123 #define MDSS_AD_MODE_CALIB 0xF 1124 1125 #define MDP_PP_AD_INIT 0x10 1126 #define MDP_PP_AD_CFG 0x20 1127 1128 struct mdss_ad_init { 1129 uint32_t asym_lut[33]; 1130 uint32_t color_corr_lut[33]; 1131 uint8_t i_control[2]; 1132 uint16_t black_lvl; 1133 uint16_t white_lvl; 1134 uint8_t var; 1135 uint8_t limit_ampl; 1136 uint8_t i_dither; 1137 uint8_t slope_max; 1138 uint8_t slope_min; 1139 uint8_t dither_ctl; 1140 uint8_t format; 1141 uint8_t auto_size; 1142 uint16_t frame_w; 1143 uint16_t frame_h; 1144 uint8_t logo_v; 1145 uint8_t logo_h; 1146 uint32_t alpha; 1147 uint32_t alpha_base; 1148 uint32_t al_thresh; 1149 uint32_t bl_lin_len; 1150 uint32_t bl_att_len; 1151 uint32_t *bl_lin; 1152 uint32_t *bl_lin_inv; 1153 uint32_t *bl_att_lut; 1154 }; 1155 1156 #define MDSS_AD_BL_CTRL_MODE_EN 1 1157 #define MDSS_AD_BL_CTRL_MODE_DIS 0 1158 struct mdss_ad_cfg { 1159 uint32_t mode; 1160 uint32_t al_calib_lut[33]; 1161 uint16_t backlight_min; 1162 uint16_t backlight_max; 1163 uint16_t backlight_scale; 1164 uint16_t amb_light_min; 1165 uint16_t filter[2]; 1166 uint16_t calib[4]; 1167 uint8_t strength_limit; 1168 uint8_t t_filter_recursion; 1169 uint16_t stab_itr; 1170 uint32_t bl_ctrl_mode; 1171 }; 1172 1173 struct mdss_ad_bl_cfg { 1174 uint32_t bl_min_delta; 1175 uint32_t bl_low_limit; 1176 }; 1177 1178 /* ops uses standard MDP_PP_* flags */ 1179 struct mdss_ad_init_cfg { 1180 uint32_t ops; 1181 union { 1182 struct mdss_ad_init init; 1183 struct mdss_ad_cfg cfg; 1184 } params; 1185 }; 1186 1187 /* mode uses MDSS_AD_MODE_* flags */ 1188 struct mdss_ad_input { 1189 uint32_t mode; 1190 union { 1191 uint32_t amb_light; 1192 uint32_t strength; 1193 uint32_t calib_bl; 1194 } in; 1195 uint32_t output; 1196 }; 1197 1198 #define MDSS_CALIB_MODE_BL 0x1 1199 struct mdss_calib_cfg { 1200 uint32_t ops; 1201 uint32_t calib_mask; 1202 }; 1203 1204 enum { 1205 mdp_op_pcc_cfg, 1206 mdp_op_csc_cfg, 1207 mdp_op_lut_cfg, 1208 mdp_op_qseed_cfg, 1209 mdp_bl_scale_cfg, 1210 mdp_op_pa_cfg, 1211 mdp_op_pa_v2_cfg, 1212 mdp_op_dither_cfg, 1213 mdp_op_gamut_cfg, 1214 mdp_op_calib_cfg, 1215 mdp_op_ad_cfg, 1216 mdp_op_ad_input, 1217 mdp_op_calib_mode, 1218 mdp_op_calib_buffer, 1219 mdp_op_calib_dcm_state, 1220 mdp_op_max, 1221 mdp_op_pa_dither_cfg, 1222 mdp_op_ad_bl_cfg, 1223 mdp_op_pp_max = 255, 1224 }; 1225 #define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg 1226 #define mdp_op_pp_max mdp_op_pp_max 1227 1228 #define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg 1229 1230 enum { 1231 WB_FORMAT_NV12, 1232 WB_FORMAT_RGB_565, 1233 WB_FORMAT_RGB_888, 1234 WB_FORMAT_xRGB_8888, 1235 WB_FORMAT_ARGB_8888, 1236 WB_FORMAT_BGRA_8888, 1237 WB_FORMAT_BGRX_8888, 1238 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 1239 }; 1240 1241 struct msmfb_mdp_pp { 1242 uint32_t op; 1243 union { 1244 struct mdp_pcc_cfg_data pcc_cfg_data; 1245 struct mdp_csc_cfg_data csc_cfg_data; 1246 struct mdp_lut_cfg_data lut_cfg_data; 1247 struct mdp_qseed_cfg_data qseed_cfg_data; 1248 struct mdp_bl_scale_data bl_scale_data; 1249 struct mdp_pa_cfg_data pa_cfg_data; 1250 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 1251 struct mdp_dither_cfg_data dither_cfg_data; 1252 struct mdp_gamut_cfg_data gamut_cfg_data; 1253 struct mdp_calib_config_data calib_cfg; 1254 struct mdss_ad_init_cfg ad_init_cfg; 1255 struct mdss_calib_cfg mdss_calib_cfg; 1256 struct mdss_ad_input ad_input; 1257 struct mdp_calib_config_buffer calib_buffer; 1258 struct mdp_calib_dcm_state calib_dcm; 1259 struct mdss_ad_bl_cfg ad_bl_cfg; 1260 } data; 1261 }; 1262 1263 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1264 enum { 1265 metadata_op_none, 1266 metadata_op_base_blend, 1267 metadata_op_frame_rate, 1268 metadata_op_vic, 1269 metadata_op_wb_format, 1270 metadata_op_wb_secure, 1271 metadata_op_get_caps, 1272 metadata_op_crc, 1273 metadata_op_get_ion_fd, 1274 metadata_op_max 1275 }; 1276 1277 struct mdp_blend_cfg { 1278 uint32_t is_premultiplied; 1279 }; 1280 1281 struct mdp_mixer_cfg { 1282 uint32_t writeback_format; 1283 uint32_t alpha; 1284 }; 1285 1286 struct mdss_hw_caps { 1287 uint32_t mdp_rev; 1288 uint8_t rgb_pipes; 1289 uint8_t vig_pipes; 1290 uint8_t dma_pipes; 1291 uint8_t max_smp_cnt; 1292 uint8_t smp_per_pipe; 1293 uint32_t features; 1294 }; 1295 1296 struct msmfb_metadata { 1297 uint32_t op; 1298 uint32_t flags; 1299 union { 1300 struct mdp_misr misr_request; 1301 struct mdp_blend_cfg blend_cfg; 1302 struct mdp_mixer_cfg mixer_cfg; 1303 uint32_t panel_frame_rate; 1304 uint32_t video_info_code; 1305 struct mdss_hw_caps caps; 1306 uint8_t secure_en; 1307 int fbmem_ionfd; 1308 } data; 1309 }; 1310 1311 #define MDP_MAX_FENCE_FD 32 1312 #define MDP_BUF_SYNC_FLAG_WAIT 1 1313 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1314 1315 struct mdp_buf_sync { 1316 uint32_t flags; 1317 uint32_t acq_fen_fd_cnt; 1318 uint32_t session_id; 1319 int *acq_fen_fd; 1320 int *rel_fen_fd; 1321 int *retire_fen_fd; 1322 }; 1323 1324 struct mdp_async_blit_req_list { 1325 struct mdp_buf_sync sync; 1326 uint32_t count; 1327 struct mdp_blit_req req[]; 1328 }; 1329 1330 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1331 1332 struct mdp_display_commit { 1333 uint32_t flags; 1334 uint32_t wait_for_finish; 1335 struct fb_var_screeninfo var; 1336 /* 1337 * user needs to follow guidelines as per below rules 1338 * 1. source split is enabled: l_roi = roi and r_roi = 0 1339 * 2. source split is disabled: 1340 * 2.1 split display: l_roi = l_roi and r_roi = r_roi 1341 * 2.2 non split display: l_roi = roi and r_roi = 0 1342 */ 1343 struct mdp_rect l_roi; 1344 struct mdp_rect r_roi; 1345 }; 1346 1347 /** 1348 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1349 * @num_overlays: Number of overlay layers as part of the frame. 1350 * @overlay_list: Pointer to a list of overlay structures identifying 1351 * the layers as part of the frame 1352 * @flags: Flags can be used to extend behavior. 1353 * @processed_overlays: Output parameter indicating how many pipes were 1354 * successful. If there are no errors this number should 1355 * match num_overlays. Otherwise it will indicate the last 1356 * successful index for overlay that couldn't be set. 1357 */ 1358 struct mdp_overlay_list { 1359 uint32_t num_overlays; 1360 struct mdp_overlay **overlay_list; 1361 uint32_t flags; 1362 uint32_t processed_overlays; 1363 }; 1364 1365 struct mdp_page_protection { 1366 uint32_t page_protection; 1367 }; 1368 1369 1370 struct mdp_mixer_info { 1371 int pndx; 1372 int pnum; 1373 int ptype; 1374 int mixer_num; 1375 int z_order; 1376 }; 1377 1378 #define MAX_PIPE_PER_MIXER 7 1379 1380 struct msmfb_mixer_info_req { 1381 int mixer_num; 1382 int cnt; 1383 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1384 }; 1385 1386 enum { 1387 DISPLAY_SUBSYSTEM_ID, 1388 ROTATOR_SUBSYSTEM_ID, 1389 }; 1390 1391 enum { 1392 MDP_IOMMU_DOMAIN_CP, 1393 MDP_IOMMU_DOMAIN_NS, 1394 }; 1395 1396 enum { 1397 MDP_WRITEBACK_MIRROR_OFF, 1398 MDP_WRITEBACK_MIRROR_ON, 1399 MDP_WRITEBACK_MIRROR_PAUSE, 1400 MDP_WRITEBACK_MIRROR_RESUME, 1401 }; 1402 1403 enum mdp_color_space { 1404 MDP_CSC_ITU_R_601, 1405 MDP_CSC_ITU_R_601_FR, 1406 MDP_CSC_ITU_R_709, 1407 }; 1408 1409 /* 1410 * These definitions are a continuation of the mdp_color_space enum above 1411 */ 1412 #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1413 #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1414 enum { 1415 mdp_igc_v1_7 = 1, 1416 mdp_igc_vmax, 1417 mdp_hist_lut_v1_7, 1418 mdp_hist_lut_vmax, 1419 mdp_pgc_v1_7, 1420 mdp_pgc_vmax, 1421 mdp_dither_v1_7, 1422 mdp_dither_vmax, 1423 mdp_gamut_v1_7, 1424 mdp_gamut_vmax, 1425 mdp_pa_v1_7, 1426 mdp_pa_vmax, 1427 mdp_pcc_v1_7, 1428 mdp_pcc_vmax, 1429 mdp_pp_legacy, 1430 mdp_dither_pa_v1_7, 1431 mdp_igc_v3, 1432 mdp_pp_unknown = 255 1433 }; 1434 1435 #define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 1436 #define mdp_pp_unknown mdp_pp_unknown 1437 #define mdp_igc_v3 mdp_igc_v3 1438 1439 /* PP Features */ 1440 enum { 1441 IGC = 1, 1442 PCC, 1443 GC, 1444 PA, 1445 GAMUT, 1446 DITHER, 1447 QSEED, 1448 HIST_LUT, 1449 HIST, 1450 PP_FEATURE_MAX, 1451 PA_DITHER, 1452 PP_MAX_FEATURES = 25, 1453 }; 1454 1455 #define PA_DITHER PA_DITHER 1456 #define PP_MAX_FEATURES PP_MAX_FEATURES 1457 1458 struct mdp_pp_feature_version { 1459 uint32_t pp_feature; 1460 uint32_t version_info; 1461 }; 1462 #endif /* _MSM_MDP_H_*/ 1463