/art/compiler/optimizing/ |
D | code_generator_arm64.cc | 346 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg())); in EmitNativeCode() 370 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode() 471 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode() 638 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(out_.reg())); in EmitNativeCode() 666 DCHECK(locations->GetLiveRegisters()->ContainsCoreRegister(index_.reg())); in EmitNativeCode() 667 if (codegen->IsCoreCalleeSaveRegister(index_.reg())) { in EmitNativeCode() 803 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(out_.reg())); in EmitNativeCode() 1386 Register reg = Register(VIXLRegCodeFromART(reg_id), kXRegSize); in SaveCoreRegister() local 1387 __ Str(reg, MemOperand(sp, stack_index)); in SaveCoreRegister() 1392 Register reg = Register(VIXLRegCodeFromART(reg_id), kXRegSize); in RestoreCoreRegister() local [all …]
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D | code_generator_arm_vixl.cc | 547 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg())); in EmitNativeCode() 572 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode() 604 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode() 1016 void CodeGeneratorARMVIXL::DumpCoreRegister(std::ostream& stream, int reg) const { in DumpCoreRegister() 1017 stream << vixl32::Register(reg); in DumpCoreRegister() 1020 void CodeGeneratorARMVIXL::DumpFloatingPointRegister(std::ostream& stream, int reg) const { in DumpFloatingPointRegister() 1021 stream << vixl32::SRegister(reg); in DumpFloatingPointRegister() 2179 for (vixl32::Register reg : kParameterCoreRegistersVIXL) { in GenerateFrameEntry() local 2180 DCHECK(!reg.Is(r4)); in GenerateFrameEntry() 7177 void ParallelMoveResolverARMVIXL::Exchange(vixl32::Register reg, int mem) { in Exchange() argument [all …]
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D | code_generator_vector_arm64_sve.cc | 1400 VRegister reg = VRegisterFrom(locations->Out()); in VisitVecLoad() local 1422 __ Uxtl(reg.V8H(), reg.V8B()); in VisitVecLoad() 1429 __ Ldr(reg, in VisitVecLoad() 1444 __ Ldr(reg, in VisitVecLoad() 1460 VRegister reg = VRegisterFrom(locations->InAt(2)); in VisitVecStore() local 1476 __ Str(reg, in VisitVecStore()
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D | code_generator_vector_arm64_neon.cc | 1400 VRegister reg = VRegisterFrom(locations->Out()); in VisitVecLoad() local 1422 __ Uxtl(reg.V8H(), reg.V8B()); in VisitVecLoad() 1429 __ Ldr(reg, in VisitVecLoad() 1444 __ Ldr(reg, in VisitVecLoad() 1460 VRegister reg = VRegisterFrom(locations->InAt(2)); in VisitVecStore() local 1476 __ Str(reg, in VisitVecStore()
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D | code_generator.cc | 935 DCHECK(is_out || !blocked_core_registers_[location.reg()]); in BlockIfInRegister() 936 blocked_core_registers_[location.reg()] = true; in BlockIfInRegister() 938 DCHECK(is_out || !blocked_fpu_registers_[location.reg()]); in BlockIfInRegister() 939 blocked_fpu_registers_[location.reg()] = true; in BlockIfInRegister() 1420 int id = location.reg(); in EmitVRegInfo() 1441 int id = location.reg(); in EmitVRegInfo()
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D | intrinsics_arm64.cc | 121 DCHECK_NE(tmp_.reg(), LR); in EmitNativeCode() 122 DCHECK_NE(tmp_.reg(), WSP); in EmitNativeCode() 123 DCHECK_NE(tmp_.reg(), WZR); in EmitNativeCode() 127 DCHECK_NE(LocationFrom(src_curr_addr).reg(), IP0); in EmitNativeCode() 128 DCHECK_NE(LocationFrom(dst_curr_addr).reg(), IP0); in EmitNativeCode() 129 DCHECK_NE(LocationFrom(src_stop_addr).reg(), IP0); in EmitNativeCode() 130 DCHECK_NE(tmp_.reg(), IP0); in EmitNativeCode() 131 DCHECK(0 <= tmp_.reg() && tmp_.reg() < kNumberOfWRegisters) << tmp_.reg(); in EmitNativeCode() 135 Thread::ReadBarrierMarkEntryPointsOffset<kArm64PointerSize>(tmp_.reg()); in EmitNativeCode() 2655 DCHECK_NE(LocationFrom(tmp).reg(), IP0); in VisitSystemArrayCopy()
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D | intrinsics_x86.cc | 2106 static void SwapBits(Register reg, Register temp, int32_t shift, int32_t mask, in SwapBits() argument 2110 __ movl(temp, reg); in SwapBits() 2111 __ shrl(reg, imm_shift); in SwapBits() 2113 __ andl(reg, imm_mask); in SwapBits() 2115 __ orl(reg, temp); in SwapBits() 2122 Register reg = locations->InAt(0).AsRegister<Register>(); in VisitIntegerReverse() local 2134 __ bswapl(reg); in VisitIntegerReverse() 2135 SwapBits(reg, temp, 1, 0x55555555, assembler); in VisitIntegerReverse() 2136 SwapBits(reg, temp, 2, 0x33333333, assembler); in VisitIntegerReverse() 2137 SwapBits(reg, temp, 4, 0x0f0f0f0f, assembler); in VisitIntegerReverse()
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D | graph_visualizer.cc | 292 codegen_.DumpCoreRegister(stream, location.reg()); in DumpLocation() 294 codegen_.DumpFloatingPointRegister(stream, location.reg()); in DumpLocation()
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D | register_allocation_resolver.cc | 400 locations->SetRegisterBit(source.reg()); in ConnectSiblings()
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/art/runtime/gc/space/ |
D | region_space.cc | 833 Region* reg = ®ions_[i]; in DumpNonFreeRegions() local 834 if (!reg->IsFree()) { in DumpNonFreeRegions() 835 reg->Dump(os); in DumpNonFreeRegions()
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/art/runtime/ |
D | thread.cc | 3709 for (size_t reg = 0; reg < num_regs; ++reg) { in VisitShadowFrame() local 3710 mirror::Object* ref = shadow_frame->GetVRegReference(reg); in VisitShadowFrame() 3713 visitor_(&new_ref, reg, this); in VisitShadowFrame() 3715 shadow_frame->SetVRegReference(reg, new_ref); in VisitShadowFrame() 3776 for (size_t reg = 0; reg < num_regs; ++reg) { in VisitNterpFrame() local 3777 StackReference<mirror::Object>* ref_addr = vreg_ref_base + reg; in VisitNterpFrame() 3781 visitor_(&new_ref, reg, this); in VisitNterpFrame() 3784 StackReference<mirror::Object>* int_addr = vreg_int_base + reg; in VisitNterpFrame()
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D | thread.h | 752 static constexpr int32_t ReadBarrierMarkEntryPointsOffset(size_t reg) { in ReadBarrierMarkEntryPointsOffset() argument 754 DCHECK_LT(reg, 30u); in ReadBarrierMarkEntryPointsOffset() 758 + static_cast<size_t>(pointer_size) * reg; in ReadBarrierMarkEntryPointsOffset()
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D | stack_map.h | 53 std::ostream& operator<<(std::ostream& stream, const DexRegisterLocation& reg);
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/art/tools/dexanalyze/ |
D | dexanalyze_bytecode.cc | 428 uint32_t reg = inst->VRegA_21t(); in ProcessCodeItem() local 432 InstNibbles(opcode, {reg, static_cast<uint16_t>(offset)})) { in ProcessCodeItem()
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/art/runtime/interpreter/ |
D | interpreter_common.h | 177 for (const auto& reg : locks) { in UnlockHeldMonitors() local 178 if (UNLIKELY(reg.dex_registers.empty())) { in UnlockHeldMonitors() 184 self, shadow_frame, shadow_frame->GetVRegReference(*reg.dex_registers.begin())); in UnlockHeldMonitors()
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/art/test/dexdump/ |
D | values.txt | 351 0x0000 - 0x0004 reg=0 this LTest;
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/art/runtime/interpreter/mterp/x86_64ng/ |
D | main.S | 238 .macro CLEAR_VOLATILE_MARKER reg argument 239 andq MACRO_LITERAL(-2), \reg
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/art/ |
D | TEST_MAPPING | 285 "name": "art-run-test-128-reg-spill-on-implicit-nullcheck"
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