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Searched refs:Register (Results 1 – 25 of 82) sorted by relevance

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/art/compiler/utils/x86/
Dassembler_x86.h60 Register rm() const { in rm()
61 return static_cast<Register>(encoding_at(0) & 7); in rm()
68 Register index() const { in index()
69 return static_cast<Register>((encoding_at(1) >> 3) & 7); in index()
72 Register base() const { in base()
73 return static_cast<Register>(encoding_at(1) & 7); in base()
88 bool IsRegister(Register reg) const { in IsRegister()
97 void SetModRM(int mod_in, Register rm_in) { in SetModRM()
103 void SetSIB(ScaleFactor scale_in, Register index_in, Register base_in) { in SetSIB()
138 explicit Operand(Register reg) : fixup_(nullptr) { SetModRM(3, reg); } in Operand()
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Dassembler_x86.cc69 void X86Assembler::call(Register reg) { in call()
102 void X86Assembler::pushl(Register reg) { in pushl()
127 void X86Assembler::popl(Register reg) { in popl()
140 void X86Assembler::movl(Register dst, const Immediate& imm) { in movl()
147 void X86Assembler::movl(Register dst, Register src) { in movl()
154 void X86Assembler::movl(Register dst, const Address& src) { in movl()
161 void X86Assembler::movl(const Address& dst, Register src) { in movl()
182 void X86Assembler::movntl(const Address& dst, Register src) { in movntl()
189 void X86Assembler::blsi(Register dst, Register src) { in blsi()
203 void X86Assembler::blsmsk(Register dst, Register src) { in blsmsk()
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Dmanaged_register_x86.cc42 Register low;
43 Register high;
68 Register low = AsRegisterPairLow(); in Overlaps()
69 Register high = AsRegisterPairHigh(); in Overlaps()
Dmanaged_register_x86.h97 constexpr Register AsCpuRegister() const { in AsCpuRegister()
99 return static_cast<Register>(id_); in AsCpuRegister()
113 constexpr Register AsRegisterPairLow() const { in AsRegisterPairLow()
119 constexpr Register AsRegisterPairHigh() const { in AsRegisterPairHigh()
162 static constexpr X86ManagedRegister FromCpuRegister(Register r) { in FromCpuRegister()
/art/compiler/utils/arm/
Dassembler_arm_vixl.h43 inline dwarf::Reg DWARFReg(vixl32::Register reg) { in DWARFReg()
69 void CompareAndBranchIfZero(vixl32::Register rn,
72 void CompareAndBranchIfNonZero(vixl32::Register rn,
86 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
111 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
122 void Rrx(vixl32::Register rd, vixl32::Register rn) { in Rrx()
127 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) { in Mul()
134 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add()
201 void PoisonHeapReference(vixl32::Register reg);
203 void UnpoisonHeapReference(vixl32::Register reg);
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Dassembler_arm_vixl.cc39 extern const vixl32::Register tr(TR);
41 extern const vixl32::Register mr(MR);
61 void ArmVIXLAssembler::PoisonHeapReference(vixl::aarch32::Register reg) { in PoisonHeapReference()
66 void ArmVIXLAssembler::UnpoisonHeapReference(vixl::aarch32::Register reg) { in UnpoisonHeapReference()
71 void ArmVIXLAssembler::MaybePoisonHeapReference(vixl32::Register reg) { in MaybePoisonHeapReference()
77 void ArmVIXLAssembler::MaybeUnpoisonHeapReference(vixl32::Register reg) { in MaybeUnpoisonHeapReference()
83 void ArmVIXLAssembler::GenerateMarkingRegisterCheck(vixl32::Register temp, int code) { in GenerateMarkingRegisterCheck()
99 void ArmVIXLAssembler::LoadImmediate(vixl32::Register rd, int32_t value) { in LoadImmediate()
148 vixl32::Register temp, in AdjustLoadStoreOffset()
149 vixl32::Register base, in AdjustLoadStoreOffset()
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Dmanaged_register_arm.h88 constexpr Register AsCoreRegister() const { in AsCoreRegister()
90 return static_cast<Register>(id_); in AsCoreRegister()
117 Register reg_low = AsRegisterPairLow(); in AsRegisterPair()
125 constexpr Register AsRegisterPairLow() const { in AsRegisterPairLow()
131 constexpr Register AsRegisterPairHigh() const { in AsRegisterPairHigh()
185 static constexpr ArmManagedRegister FromCoreRegister(Register r) { in FromCoreRegister()
207 static constexpr ArmManagedRegister FromCoreRegisterPair(Register r_low) { in FromCoreRegisterPair()
Djni_macro_assembler_arm_vixl.cc47 vixl::aarch32::Register AsVIXLRegister(ArmManagedRegister reg) { in AsVIXLRegister()
49 return vixl::aarch32::Register(reg.RegId()); in AsVIXLRegister()
62 static inline vixl::aarch32::Register AsVIXLRegisterPairLow(ArmManagedRegister reg) { in AsVIXLRegisterPairLow()
63 return vixl::aarch32::Register(reg.AsRegisterPairLow()); in AsVIXLRegisterPairLow()
66 static inline vixl::aarch32::Register AsVIXLRegisterPairHigh(ArmManagedRegister reg) { in AsVIXLRegisterPairHigh()
67 return vixl::aarch32::Register(reg.AsRegisterPairHigh()); in AsVIXLRegisterPairHigh()
185 vixl32::Register temp = temps.Acquire(); in RemoveFrame()
243 vixl::aarch32::Register src = AsVIXLRegister(msrc.AsArm()); in StoreRef()
250 vixl::aarch32::Register src = AsVIXLRegister(msrc.AsArm()); in StoreRawPtr()
259 vixl::aarch32::Register src = AsVIXLRegister(msrc.AsArm()); in StoreSpanning()
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/art/compiler/optimizing/
Dintrinsics_x86.cc93 Register src = locations->InAt(0).AsRegister<Register>(); in EmitNativeCode()
95 Register dest = locations->InAt(2).AsRegister<Register>(); in EmitNativeCode()
99 Register temp1 = temp1_loc.AsRegister<Register>(); in EmitNativeCode()
100 Register temp2 = locations->GetTemp(1).AsRegister<Register>(); in EmitNativeCode()
101 Register temp3 = locations->GetTemp(2).AsRegister<Register>(); in EmitNativeCode()
124 __ leal(temp2, Address(src_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0)); in EmitNativeCode()
147 __ leal(temp3, Address(dest_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0)); in EmitNativeCode()
196 __ movd(output.AsRegisterPairLow<Register>(), temp); in MoveFPToInt()
198 __ movd(output.AsRegisterPairHigh<Register>(), temp); in MoveFPToInt()
200 __ movd(output.AsRegister<Register>(), input.AsFpuRegister<XmmRegister>()); in MoveFPToInt()
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Dcode_generator_x86.cc51 static constexpr Register kMethodRegisterArgument = EAX;
52 static constexpr Register kCoreCalleeSaves[] = { EBP, ESI, EDI };
56 static constexpr int kFakeReturnRegister = Register(8);
121 DivRemMinusOneSlowPathX86(HInstruction* instruction, Register reg, bool is_div) in DivRemMinusOneSlowPathX86()
137 Register reg_;
166 Address array_len(array_loc.AsRegister<Register>(), len_offset); in EmitNativeCode()
173 __ movl(length_loc.AsRegister<Register>(), array_len); in EmitNativeCode()
175 __ shrl(length_loc.AsRegister<Register>(), Immediate(1)); in EmitNativeCode()
340 __ UnpoisonHeapReference(locations->InAt(1).AsRegister<Register>()); in EmitNativeCode()
481 Register ref_reg = ref_.AsRegister<Register>(); in EmitNativeCode()
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Dcode_generator_x86.h37 static constexpr Register kParameterCoreRegisters[] = { ECX, EDX, EBX };
43 static constexpr Register kRuntimeParameterCoreRegisters[] = { EAX, ECX, EDX, EBX };
50 class InvokeRuntimeCallingConvention : public CallingConvention<Register, XmmRegister> {
63 class InvokeDexCallingConvention : public CallingConvention<Register, XmmRegister> {
164 void Exchange(Register reg, int mem);
240 void GenerateClassInitializationCheck(SlowPathCode* slow_path, Register class_reg);
241 void GenerateBitstringTypeCheckCompare(HTypeCheckInstruction* check, Register temp);
251 void GenerateShlLong(const Location& loc, Register shifter);
252 void GenerateShrLong(const Location& loc, Register shifter);
253 void GenerateUShrLong(const Location& loc, Register shifter);
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Dcommon_arm.h40 inline vixl::aarch32::Register HighRegisterFrom(Location location) { in HighRegisterFrom()
42 return vixl::aarch32::Register(location.AsRegisterPairHigh<vixl::aarch32::Register>()); in HighRegisterFrom()
50 inline vixl::aarch32::Register LowRegisterFrom(Location location) { in LowRegisterFrom()
52 return vixl::aarch32::Register(location.AsRegisterPairLow<vixl::aarch32::Register>()); in LowRegisterFrom()
65 inline vixl::aarch32::Register RegisterFrom(Location location) { in RegisterFrom()
67 return vixl::aarch32::Register(location.reg()); in RegisterFrom()
70 inline vixl::aarch32::Register RegisterFrom(Location location, DataType::Type type) { in RegisterFrom()
135 inline vixl::aarch32::Register OutputRegister(HInstruction* instr) { in OutputRegister()
139 inline vixl::aarch32::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt()
144 inline vixl::aarch32::Register InputRegister(HInstruction* instr) { in InputRegister()
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Dcode_generator_arm_vixl.h51 static const vixl::aarch32::Register kParameterCoreRegistersVIXL[] = {
77 static const vixl::aarch32::Register kMethodRegister = vixl::aarch32::r0;
97 static const vixl::aarch32::Register kRuntimeParameterCoreRegistersVIXL[] = {
147 : public CallingConvention<vixl::aarch32::Register, vixl::aarch32::SRegister> {
161 : public CallingConvention<vixl::aarch32::Register, vixl::aarch32::SRegister> {
277 void Exchange(vixl32::Register reg, int mem);
351 vixl32::Register class_reg);
353 vixl::aarch32::Register temp,
355 void GenerateAndConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value);
356 void GenerateOrrConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value);
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Dintrinsics_arm_vixl.cc76 const vixl32::Register& array, in GenSystemArrayCopyBaseAddress()
78 const vixl32::Register& base) { in GenSystemArrayCopyBaseAddress()
100 const vixl32::Register& base, in GenSystemArrayCopyEndAddress()
101 const vixl32::Register& end) { in GenSystemArrayCopyEndAddress()
140 vixl32::Register dest = InputRegisterAt(instruction_, 2); in EmitNativeCode()
142 vixl32::Register src_curr_addr = RegisterFrom(locations->GetTemp(0)); in EmitNativeCode()
143 vixl32::Register dst_curr_addr = RegisterFrom(locations->GetTemp(1)); in EmitNativeCode()
144 vixl32::Register src_stop_addr = RegisterFrom(locations->GetTemp(2)); in EmitNativeCode()
145 vixl32::Register tmp = RegisterFrom(locations->GetTemp(3)); in EmitNativeCode()
298 vixl32::Register out = RegisterFrom(locations->Out()); in GenNumberOfLeadingZeros()
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Dcommon_arm64.h66 inline vixl::aarch64::Register XRegisterFrom(Location location) { in XRegisterFrom()
68 return vixl::aarch64::Register::GetXRegFromCode(VIXLRegCodeFromART(location.reg())); in XRegisterFrom()
71 inline vixl::aarch64::Register WRegisterFrom(Location location) { in WRegisterFrom()
73 return vixl::aarch64::Register::GetWRegFromCode(VIXLRegCodeFromART(location.reg())); in WRegisterFrom()
76 inline vixl::aarch64::Register RegisterFrom(Location location, DataType::Type type) { in RegisterFrom()
81 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) { in OutputRegister()
85 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt()
153 ? vixl::aarch64::Register(vixl::aarch64::xzr) in InputCPURegisterOrZeroRegAt()
154 : vixl::aarch64::Register(vixl::aarch64::wzr); in InputCPURegisterOrZeroRegAt()
180 inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base,
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Dintrinsics_arm64.cc104 Register src_curr_addr = XRegisterFrom(locations->GetTemp(0)); in EmitNativeCode()
105 Register dst_curr_addr = XRegisterFrom(locations->GetTemp(1)); in EmitNativeCode()
106 Register src_stop_addr = XRegisterFrom(locations->GetTemp(2)); in EmitNativeCode()
107 Register tmp_reg = WRegisterFrom(tmp_); in EmitNativeCode()
370 Register src = InputRegisterAt(instr, 0); in GenBitCount()
371 Register dst = RegisterFrom(instr->GetLocations()->Out(), type); in GenBitCount()
401 Register src = InputRegisterAt(invoke, 0); in GenHighestOneBit()
402 Register dst = RegisterFrom(invoke->GetLocations()->Out(), type); in GenHighestOneBit()
403 Register temp = (type == DataType::Type::kInt64) ? temps.AcquireX() : temps.AcquireW(); in GenHighestOneBit()
434 Register src = InputRegisterAt(invoke, 0); in GenLowestOneBit()
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Dcode_generator_arm_vixl.cc108 static inline bool CanEmitNarrowLdr(vixl32::Register rt, vixl32::Register rn, uint32_t offset) { in CanEmitNarrowLdr()
114 EmitAdrCode(ArmVIXLMacroAssembler* assembler, vixl32::Register rd, vixl32::Label* label) in EmitAdrCode()
137 vixl32::Register rd_;
202 vixl32::Register base = sp; in SaveContiguousSRegisterList()
250 vixl32::Register base = sp; in RestoreContiguousSRegisterList()
752 vixl32::Register reg_out = RegisterFrom(out_); in EmitNativeCode()
780 vixl32::Register index_reg = RegisterFrom(index_); in EmitNativeCode()
805 vixl32::Register free_reg = FindAvailableCallerSaveRegister(codegen); in EmitNativeCode()
878 vixl32::Register FindAvailableCallerSaveRegister(CodeGenerator* codegen) { in FindAvailableCallerSaveRegister()
883 return vixl32::Register(i); in FindAvailableCallerSaveRegister()
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Dcode_generator_arm64.h59 static const vixl::aarch64::Register kParameterCoreRegisters[] = {
82 const vixl::aarch64::Register tr = vixl::aarch64::x19;
84 const vixl::aarch64::Register mr = vixl::aarch64::x20;
86 static const vixl::aarch64::Register kArtMethodRegister = vixl::aarch64::x0;
157 static const vixl::aarch64::Register kRuntimeParameterCoreRegisters[] =
180 class InvokeRuntimeCallingConvention : public CallingConvention<vixl::aarch64::Register,
198 class InvokeDexCallingConvention : public CallingConvention<vixl::aarch64::Register,
317 vixl::aarch64::Register class_reg);
319 vixl::aarch64::Register temp);
370 void GenerateIncrementNegativeByOne(vixl::aarch64::Register out,
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Dcode_generator_arm64.cc186 Register base = masm->StackPointer(); in SaveRestoreLiveRegistersHelper()
196 Register new_base = temps.AcquireSameSizeAs(base); in SaveRestoreLiveRegistersHelper()
665 Register index_reg = RegisterFrom(index_, DataType::Type::kInt32); in EmitNativeCode()
690 Register free_reg = FindAvailableCallerSaveRegister(codegen); in EmitNativeCode()
762 Register FindAvailableCallerSaveRegister(CodeGenerator* codegen) { in FindAvailableCallerSaveRegister()
767 return Register(VIXLRegCodeFromART(i), kXRegSize); in FindAvailableCallerSaveRegister()
1131 Register counter = temps.AcquireX(); in MaybeIncrementHotness()
1132 Register method = is_frame_entry ? kArtMethodRegister : temps.AcquireX(); in MaybeIncrementHotness()
1150 Register temp = temps.AcquireX(); in MaybeIncrementHotness()
1151 Register counter = temps.AcquireW(); in MaybeIncrementHotness()
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/art/compiler/utils/arm64/
Dassembler_arm64.h109 void PoisonHeapReference(vixl::aarch64::Register reg);
111 void UnpoisonHeapReference(vixl::aarch64::Register reg);
113 void MaybePoisonHeapReference(vixl::aarch64::Register reg);
115 void MaybeUnpoisonHeapReference(vixl::aarch64::Register reg);
124 void GenerateMarkingRegisterCheck(vixl::aarch64::Register temp, int code = 0);
140 static vixl::aarch64::Register reg_x(int code) { in reg_x()
147 return vixl::aarch64::Register::GetXRegFromCode(code); in reg_x()
150 static vixl::aarch64::Register reg_w(int code) { in reg_w()
157 return vixl::aarch64::Register::GetWRegFromCode(code); in reg_w()
Dassembler_arm64.cc109 const Register sp = vixl_masm_.StackPointer(); in SpillRegisters()
137 const Register sp = vixl_masm_.StackPointer(); in UnspillRegisters()
161 void Arm64Assembler::PoisonHeapReference(Register reg) { in PoisonHeapReference()
167 void Arm64Assembler::UnpoisonHeapReference(Register reg) { in UnpoisonHeapReference()
173 void Arm64Assembler::MaybePoisonHeapReference(Register reg) { in MaybePoisonHeapReference()
179 void Arm64Assembler::MaybeUnpoisonHeapReference(Register reg) { in MaybeUnpoisonHeapReference()
185 void Arm64Assembler::GenerateMarkingRegisterCheck(Register temp, int code) { in GenerateMarkingRegisterCheck()
190 vixl::aarch64::Register mr = reg_x(MR); // Marking Register. in GenerateMarkingRegisterCheck()
191 vixl::aarch64::Register tr = reg_x(TR); // Thread Register. in GenerateMarkingRegisterCheck()
/art/compiler/utils/x86_64/
Dconstants_x86_64.h33 explicit constexpr CpuRegister(Register r) : reg_(r) {} in CpuRegister()
34 explicit constexpr CpuRegister(int r) : reg_(Register(r)) {} in CpuRegister()
35 constexpr Register AsRegister() const { in AsRegister()
45 const Register reg_;
Dmanaged_register_x86_64.cc41 Register low;
42 Register high;
63 Register low = AsRegisterPairLow().AsRegister(); in Overlaps()
64 Register high = AsRegisterPairHigh().AsRegister(); in Overlaps()
/art/runtime/arch/x86/
Dregisters_x86.h27 enum Register { enum
40 std::ostream& operator<<(std::ostream& os, const Register& rhs);
/art/runtime/arch/x86_64/
Dregisters_x86_64.h27 enum Register { enum
48 std::ostream& operator<<(std::ostream& os, const Register& rhs);

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