/art/compiler/optimizing/ |
D | intrinsics_arm_vixl.cc | 44 using helpers::InputRegisterAt; 140 vixl32::Register dest = InputRegisterAt(instruction_, 2); in EmitNativeCode() 517 __ Strb(InputRegisterAt(invoke, 1), MemOperand(LowRegisterFrom(invoke->GetLocations()->InAt(0)))); in VisitMemoryPokeByte() 526 __ Str(InputRegisterAt(invoke, 1), MemOperand(LowRegisterFrom(invoke->GetLocations()->InAt(0)))); in VisitMemoryPokeIntNative() 549 __ Strh(InputRegisterAt(invoke, 1), MemOperand(LowRegisterFrom(invoke->GetLocations()->InAt(0)))); in VisitMemoryPokeShortNative() 571 vixl32::Register base = InputRegisterAt(invoke, 1); // Object pointer. in GenUnsafeGet() 930 vixl32::Register base = InputRegisterAt(instruction_, 1); // Object pointer. in EmitNativeCode() 932 vixl32::Register expected = InputRegisterAt(instruction_, 3); // Expected. in EmitNativeCode() 933 vixl32::Register value = InputRegisterAt(instruction_, 4); // Value. in EmitNativeCode() 992 vixl32::Register base = InputRegisterAt(invoke, 1); // Object pointer. in GenCas() [all …]
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D | code_generator_arm64.cc | 71 using helpers::InputRegisterAt; 2022 MemOperand field = HeapOperand(InputRegisterAt(instruction, 0), field_info.GetFieldOffset()); in HandleFieldGet() 2082 Register obj = InputRegisterAt(instruction, 0); in HandleFieldSet() 2124 Register lhs = InputRegisterAt(instr, 0); in HandleBinaryOp() 2203 Register lhs = InputRegisterAt(instr, 0); in HandleShift() 2260 Register lhs = InputRegisterAt(instr, 0); in VisitBitwiseNegatedRight() 2261 Register rhs = InputRegisterAt(instr, 1); in VisitBitwiseNegatedRight() 2301 left = InputRegisterAt(instruction, 0); in VisitDataProcWithShifterOp() 2362 InputRegisterAt(instruction, 0), in VisitIntermediateAddress() 2386 Register index_reg = InputRegisterAt(instruction, 0); in VisitIntermediateAddressIndex() [all …]
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D | common_arm.h | 139 inline vixl::aarch32::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt() function 146 return InputRegisterAt(instr, 0); in InputRegister()
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D | code_generator_arm_vixl.cc | 56 using helpers::InputRegisterAt; 1519 __ Cmp(InputRegisterAt(condition, 0), InputOperandAt(condition, 1)); in GenerateTest() 1685 vixl32::Register in = InputRegisterAt(cond, 0); in GenerateConditionIntegralOrNonPrimitive() 2727 __ CompareAndBranchIfZero(InputRegisterAt(instruction, condition_input_index), in GenerateTestAndBranch() 2731 __ CompareAndBranchIfNonZero(InputRegisterAt(instruction, condition_input_index), in GenerateTestAndBranch() 2750 const vixl32::Register left = InputRegisterAt(cond, 0); in GenerateTestAndBranch() 2918 __ Cmp(InputRegisterAt(select, 2), 0); in VisitSelect() 3132 vixl32::Register left = InputRegisterAt(cond, 0); in HandleCondition() 3591 __ Rsb(OutputRegister(neg), InputRegisterAt(neg, 0), 0); in VisitNeg() 3785 __ Ubfx(OutputRegister(conversion), InputRegisterAt(conversion, 0), 0, 8); in VisitTypeConversion() [all …]
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D | code_generator_vector_arm_vixl.cc | 29 using helpers::InputRegisterAt; 62 __ Vdup(Untyped8, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar() 67 __ Vdup(Untyped16, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar() 71 __ Vdup(Untyped32, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar() 780 __ Vmov(Untyped32, DRegisterLane(dst, 0), InputRegisterAt(instruction, 0)); in VisitVecSetScalars() 905 vixl32::Register base = InputRegisterAt(instruction, 0); in VecAddress() 931 vixl32::Register base = InputRegisterAt(instruction, 0); in VecAddressUnaligned()
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D | common_arm64.h | 85 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt() function 144 : static_cast<vixl::aarch64::CPURegister>(InputRegisterAt(instr, index)); in InputCPURegisterAt()
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D | code_generator_vector_arm64_sve.cc | 32 using helpers::InputRegisterAt; 91 __ Dup(dst.V16B(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar() 100 __ Dup(dst.V8H(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar() 108 __ Dup(dst.V4S(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar() 1016 __ Mov(dst.V16B(), 0, InputRegisterAt(instruction, 0)); in VisitVecSetScalars() 1021 __ Mov(dst.V8H(), 0, InputRegisterAt(instruction, 0)); in VisitVecSetScalars() 1025 __ Mov(dst.V4S(), 0, InputRegisterAt(instruction, 0)); in VisitVecSetScalars() 1029 __ Mov(dst.V2D(), 0, InputRegisterAt(instruction, 0)); in VisitVecSetScalars() 1416 __ Ldr(length, HeapOperand(InputRegisterAt(instruction, 0), count_offset)); in VisitVecLoad()
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D | code_generator_vector_arm64_neon.cc | 32 using helpers::InputRegisterAt; 91 __ Dup(dst.V16B(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar() 100 __ Dup(dst.V8H(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar() 108 __ Dup(dst.V4S(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar() 1016 __ Mov(dst.V16B(), 0, InputRegisterAt(instruction, 0)); in VisitVecSetScalars() 1021 __ Mov(dst.V8H(), 0, InputRegisterAt(instruction, 0)); in VisitVecSetScalars() 1025 __ Mov(dst.V4S(), 0, InputRegisterAt(instruction, 0)); in VisitVecSetScalars() 1029 __ Mov(dst.V2D(), 0, InputRegisterAt(instruction, 0)); in VisitVecSetScalars() 1416 __ Ldr(length, HeapOperand(InputRegisterAt(instruction, 0), count_offset)); in VisitVecLoad()
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D | intrinsics_arm64.cc | 58 using helpers::InputRegisterAt; 370 Register src = InputRegisterAt(instr, 0); in GenBitCount() 401 Register src = InputRegisterAt(invoke, 0); in GenHighestOneBit() 434 Register src = InputRegisterAt(invoke, 0); in GenLowestOneBit() 1125 Register str = InputRegisterAt(invoke, 0); in VisitStringCompareTo() 1126 Register arg = InputRegisterAt(invoke, 1); in VisitStringCompareTo() 2908 Register crc = InputRegisterAt(invoke, 0); in VisitCRC32Update() 2909 Register val = InputRegisterAt(invoke, 1); in VisitCRC32Update() 3149 Register bits = InputRegisterAt(invoke, 0); in VisitFP16ToFloat()
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