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Searched refs:WZR (Results 1 – 7 of 7) sorted by relevance

/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc95 wreg = Arm64ManagedRegister::FromWRegister(WZR); in TEST()
157 reg = Arm64ManagedRegister::FromWRegister(WZR); in TEST()
384 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); in TEST()
406 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); in TEST()
428 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); in TEST()
443 reg_o = Arm64ManagedRegister::FromWRegister(WZR); in TEST()
463 reg_o = Arm64ManagedRegister::FromWRegister(WZR); in TEST()
466 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); in TEST()
485 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); in TEST()
506 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); in TEST()
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Dassembler_arm64.h154 } else if (code == WZR) { in reg_w()
Dmanaged_register_arm64.h82 if (IsZeroRegister()) return WZR; in AsOverlappingWRegister()
/art/runtime/arch/arm64/
Dregisters_arm64.h107 WZR = 32, enumerator
/art/compiler/optimizing/
Dcommon_arm64.h43 static_assert((SP == 31) && (WSP == 31) && (XZR == 32) && (WZR == 32),
Dintrinsics_arm64.cc123 DCHECK_NE(tmp_.reg(), WZR); in EmitNativeCode()
Dcode_generator_arm64.cc1247 Register wzr = Register(VIXLRegCodeFromART(WZR), kWRegSize); in GenerateFrameEntry()